8-stage superscalar processor that supports ISO 26262 ASIL-D level functional safety for automotive applications
40G UCIe PHY for high-density advanced packages
High speed 3.3V I/0 Library with 8kV ESD protection in TPSCo 65nm technology
Low jitter, low-power clock-deskew PLL operating from 6GHz to 9.5GHz on GF 22nm FDX
Cryptomathic and PQShield form strategic alliance to offer PQC solutions for code signing and data protection in compliance with latest NIST and CNSA recommendations
RaaS, a collaborative initiative, adopted Menta's eFPGA technology for RaaS Edge Computing platform
Cadence Tensilica HiFi 5 DSPs Used in NXP's Next-Gen Audio DSP Family
An Introduction to Direct RF Sampling in a World Evolving Towards Chiplets - Part 1
How to cost-efficiently add Ethernet switching to industrial devices
Optimizing Analog Layouts: Techniques for Effective Layout Matching
Arasan I3C PHY - Ternary vs. Non-Ternary
Accelerating RISC-V Processor Verification: A Co-Simulation Strategy
3 steps to shrinking your code size, your costs, and your power consumption
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