32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
High-performance mixed-precision NPU IP
ASIL B Ready PCIe 5.0 Integrity and Data Encryption (IDE) Security IP
DVB-S2X Wideband LDPC BCH Decoder
Credo at TSMC 2024 North America Technology Symposium
Rambus Advances AI 2.0 with GDDR7 Memory Controller IP
RAAAM Memory Technologies Closes $4M Seed Round to Commercialize Super Cost Effective On-Chip Memory Solutions
From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
Embracing a More Secure Era with TLS 1.3
Maximizing ESD protection for automotive Ethernet applications
Integrating Coherent RISC-V SoCs: Advanced Solutions with Perspec
Semi Market Decreased by 8% in 2023... When Design IP Sales Grew by 6%!
Defacto SoC Compiler performance on AWS Graviton3
© 2024 Design And Reuse
All Rights Reserved.
No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.
Suppliers, list your IPs for free.