25-112Gbps Short-Reach PHY
Northwest Logic CSI-2 Controller Core V2 from Rambus
Tunable Hash (SHA3) accelerator
IMG A-Series AXE Graphics Processor
Update to Royalty-Free MIPI I3C Basic Utility and Control Bus Specification Boosts Speed and Flexibility
DCD-SEMI introduces octa SPI IP Core for smart wear, audio and mobile
100G MAC and 100G PCS IP Cores for high performance applications are now available
PUFiot: An Essential Secure Coprocessor for RISC-V
How PUF-based RoT Can Solve IoT Security Issues
eNVM towards 40nm and beyond
RISC-V Chiplets, Disaggregated Die, and Tiles
PCIe 5.0 Controller IP on FPGAs: Current and Future Use Cases
Why it's the perfect time to join Codasip and be part of the RISC-V revolution
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