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IP / SOC Products News

• eMemory's OTP IP Qualified on 22nm FD-SOI process (Wednesday Oct. 17, 2018)
  eMemory today announced that its one-time programmable non-volatile memory (OTP) IP, NeoFuse, has been qualified for 22nm Fully-Depleted Silicon On-Insulator (FD-SOI), also known as 22FDX, process technology.
  
  
• Arm Neoverse: The modern cloud to edge infrastructure foundation for a world of a trillion intelligent devices (Tuesday Oct. 16, 2018)
  Today at Arm TechCon, Arm disclosed details on a dedicated roadmap and new brand of infrastructure-class IP for 5G networks and next-generation cloud to edge infrastructure.
  
  
• OPENEDGES unveils world-first Memory Subsystem IP solution coupling Network-on-Chip (NoC) interconnect with DDR memory controller (Tuesday Oct. 16, 2018)
  OPENEDGES, the leading IP provider in smart computing, announced its release of cutting-edge ORBITTM Memory Subsystem IP solution combining Network-on-Chip (NoC) interconnect and DDR memory controller.
  
  
• QuickLogic Announces Silicon-Proven ArcticPro eFPGA on GLOBALFOUNDRIES 22FDX Process (Tuesday Oct. 09, 2018)
  QuickLogic today announced the availability of silicon-proven and ready-to-use ultra-low power ArcticPro™ eFPGA technology on GLOBALFOUNDRIES 22FDX® (FD-SOI) process technology.
  
  
• Andes Announces over 1.2 GHz RISC-V Cores Series at 28nm: A25/AX25 and N25F/NX25F (Monday Oct. 08, 2018)
  Andes Technology, a founding member of the RISC-V Foundation and the leading Taiwan-based supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 2.5-Billion SoCs covering a wide range of applications, today announced the availability of the latest four members of the AndeStar™ V5 high efficiency processor series.
  
  
• Northwest Logic and Mixel Delivering C-PHY/D-PHY Combo MIPI IP Solution (Thursday Oct. 04, 2018)
  Northwest Logic and Mixel® announced today that their MIPI® CSI-2SM and DSI-2SM solutions which utilize MIPI C-PHY SM / D-PHY SM have been deployed and silicon proven in 28nm, 40nm, 55nm and 65nm process nodes. These high performance, low power, cost effective solutions contain controllers from Northwest Logic and PHYs from Mixel.
  
  
• Synopsys and TSMC Collaborate to Develop Portfolio of DesignWare IP for TSMC N7+ FinFET Process (Thursday Oct. 04, 2018)
  Synopsys, Inc. (Nasdaq: SNPS) today announced a collaboration with TSMC to develop a broad portfolio of DesignWare® Interface IP, Logic Libraries and Embedded Memories for the TSMC N7+ FinFET process.
  
  
• Omnitek Demonstrates Highest Performance Convolutional Neural Network on an FPGA (Thursday Oct. 04, 2018)
  Omnitek today announced immediate availability of the highest performance CNN on an FPGA, achieving over 50% higher performance than any competing CNNs and out-performing GPUs for a given power or cost budget.
  
  
• Silicon Creations Highlights PLL Developments in 22nm, 12nm, 7nm, and 5nm at TSMC OIP Ecosystem Forum (Tuesday Oct. 02, 2018)
  Silicon Creations, a leading supplier of high-performance analog and mixed-signal intellectual property (IP), announced a wide variety of IP offerings in TSMC’s 5FF, 7FF, 7FF+, 12FFC, and 22ULP/ULL process nodes, designed to support customer’s SoC timing demands.
  
  
• M31 Technology's Diversified TSMC 28HPC+ ULL Memory Compilers Empower More Flexible SoC Design Architecture (Tuesday Oct. 02, 2018)
  M31 Technology Corporation (Taiwan stock code: 6643), a global Silicon Intellectual Property (IP) boutique, today announced that it has developed a diversified TSMC 28HPC + Ultra-Low Power (ULL) Memory Compiler IP portfolio that provides customers with more flexibility in their SoC design.
  
  
• Arm expands design possibilities with free Cortex-M processors for Xilinx FPGAs (Monday Oct. 01, 2018)
  Today at the Xilinx Developer Forum in San Jose, Arm has announced it is collaborating with Xilinx, the market leader in FPGAs, to bring the benefits of Arm Cortex-M processors to FPGA through the Arm DesignStart program, providing scalability and a standardized processor architecture across the Xilinx portfolio.
  
  
• Synopsys Delivers Automotive-Grade IP in TSMC 7-nm Process for ADAS Designs (Monday Oct. 01, 2018)
  Synopsys today announced delivery of automotive-grade DesignWare® Controller and PHY IP for TSMC's 7-nanometer (nm) FinFET process. The DesignWare LPDDR4x, MIPI CSI-2 and D-PHY, PCI Express® 4.0, and security IP implement advanced automotive design rules for TSMC 7-nm process to meet the stringent reliability and operation requirements of ADAS and autonomous driving system-on-chips (SoCs).
  
  
• Dolphin Integration accelerates the development of energy-efficient SoCs for Arm-based secure IoT devices (Monday Oct. 01, 2018)
  Dolphin Integration today announced it is collaborating with Arm to make embedded and Internet of Things (IoT) devices more efficient. By combining a set of low-power and high-efficiency voltage regulators with a range of Arm-based IoT System-on-Chip (SoC) solutions, Dolphin aims to accelerate the cost-effective design of secure, smart and energy-efficient SoCs.
  
  
• T2M announces its first Image Signal Processing (ISP) Technology for advanced mobile camera applications (Friday Sep. 28, 2018)
  T2M, the world’s largest independent global semiconductor IP provider, announced the launch of its first low-power digital image processor IP designed to perform advanced image correction and enhancement, resulting in superior image quality in today’s multi-megapixel cameras.
  
  
• M31 MIPI M-PHY is certified with ASIL-B safety level of ISO 26262 to provide safe and reliable automotive SoC design (Thursday Sep. 27, 2018)
  M31 Technology announced today that its MIPI M-PHY Gear3 IP has been certified with the ASIL B safety level of ISO 26262 and will be used by international first-class automotive electronics manufacturers to provide safe and reliable automotive SoC design.
  
  
• Arm announces new flagship IP and safety program for automotive (Wednesday Sep. 26, 2018)
  The Cortex-A76AE is a game-changing new CPU uniquely designed for automotive and optimized for 7nm process nodes. AE stands for “Automotive Enhanced” and any Arm IP with the AE designator will include specific features addressing the requirements of in-vehicle processing.
  
  
• Spectral introduces NeuralRAM, memory architectures in 14nm FinFET tech node targeted for a wide range of AI algorithms (Wednesday Sep. 26, 2018)
  Spectral Design & Test Inc. (SDT) today announced rolling out a family of Memory IP on the GlobalFoundries 14nm FinFET process that addresses the needs of the new Artificial Intelligence (AI), Machine Learning and Deep Learning SoC applications.
  
  
• Imagination and GLOBALFOUNDRIES Collaborate to Deliver Ultra-Low-Power Connectivity Solutions for IoT Applications (Tuesday Sep. 25, 2018)
  Imagination Technologies and GLOBALFOUNDRIES (GF) announced today a joint collaboration to provide ultra-low-power baseband and radio frequency (RF) solutions for Bluetooth Low Energy® (BLE) and IEEE 802.15.4 technology, using Imagination’s Ensigma connectivity IP on GF’s 22nm FD-SOI (22FDX®) platform.
  
  
• Renesas Expands Access to Robust Portfolio of IP Licenses (Thursday Sep. 20, 2018)
  Renesas Electronics Corporation today announced it is expanding access to its extensive portfolio of intellectual property (IP) licenses that allow designers to meet a broad range of customized customer requirements in a rapidly changing industry.
  
  
• Cadence Launches New Tensilica DNA 100 Processor IP Delivering Industry-Leading Performance and Power Efficiency for On-Device AI Applications (Wednesday Sep. 19, 2018)
  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Cadence® Tensilica®, the first deep neural-network accelerator (DNA) AI processor IP to deliver both high performance and power efficiency across a full range of compute from 0.5 TeraMAC (TMAC) to 100s of TMACs.
  
  
• eSilicon Announces Availability of neuASIC IP Platform for AI ASIC Design (Tuesday Sep. 18, 2018)
  eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the availability of its 7nm neuASICä IP platform for customer AI ASIC designs.
  
  
• Attopsemi's I-fuse OTP worked at 0.4V and 1uW read at 22nm process for IoT application (Monday Sep. 17, 2018)
  Attopsemi Technology Co., LTD, a leading OTP solution provider, announced today that it recently had One-Time Programmable (OTP) IP working at 0.4V and 1uW read for a battery-less 61GHz RFID tags application.
  
  
• SoC-e's 1588Tiny IP Core now supports Layer-3 PTP operation (Monday Sep. 17, 2018)
  SoCe keeps pushing the improvement of its IP Cores in order to fit the the needs of their customers. This time, we are happy to announce that the last update of the 1588Tiny IP Core adds support for Layer-3 PTP Operation.
  
  
• Arasan Announces it's 2'nd Generation MIPI C-PHY / D-PHY IP Combo Core for C-PHY v1.2 Specifications (Thursday Sep. 13, 2018)
  Arasan today announced the immediate availability of its MIPI C-PHY / D-PHY Combo IP Core compliant to the C-PHY specification Version 1.2 while also being compliant to the D-PHY 1.2 Specification.
  
  
• eSilicon Announces Silicon Validation of 7nm 56G SerDes (Thursday Sep. 13, 2018)
  eSilicon disclosed today that it has validated its 7nm 56G long-reach SerDes in silicon and that lab measurements confirm that the design is meeting or exceeding the target performance, power and functionality.
  
  
• Smartlogic announces PCI Express Multifunction IP Core for Xilinx 7 Series (Wednesday Sep. 12, 2018)
  Smartlogic today announced the immediate availability of the new 2.0 Release of the Multifunction IP Core for PCI Express®.
  
  
• Synopsys and Truphone Enable Secure Over-the-Air Provisioning with Integrated SIM IP and Managed Services Solution (Tuesday Sep. 11, 2018)
  Synopsys and Truphone today announced a collaboration to integrate Truphone's embedded SIM (eUICC) software into the DesignWare® tRoot™ Hardware Secure Module (HSM) for integrated SIM (iSIM) to protect device connectivity and management.
  
  
• Allegro DVT Introduces Industry's First HEVC SHVC Encoder IP, Pushes Video Quality to New Levels (Tuesday Sep. 11, 2018)
  Allegro DVT announced today the availability of its AL-E120 encoder IP which brings support for HEVC scalable extension (SHVC) and video quality improvement by up to 20% compared to previous Allegro DVT encoding products.
  
  
• New Synopsys HPC Design Kit Delivers Superior Performance, Power, and Area Efficiency for DesignWare Embedded Vision Processor IP (Monday Sep. 10, 2018)
  Synopsys today announced the DesignWare® High-Performance Core (HPC) Design Kit for EV6x Processors to help designers meet the performance, power, and area requirements of their systems-on-chips (SoCs) for embedded vision (EV) and artificial intelligence (AI) applications.
  
  
• SoC-e's Managed Ethernet Switch now supports up-to 32 ports (Monday Sep. 10, 2018)
  SoCe is continuously improving its products and introducing new improvements to adapt them to the needs of the market. This time we are proud to present the last evolution of one of our most demanded products, the ManagedEthernetSwitch (MES) IP Core.