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IP / SOC Products News

• intoPIX releases a new range of 8K TICO-XS IP-cores supporting the JPEG XS standard (Thursday Oct. 29, 2020)
  intoPIX, leading provider of innovative compression solutions for audio-visual applications, today announces the release, with direct availability, of 8K TICO-XS encoder and decoder IP-Cores.
  
  
• SDR RF IP, 100MHz-2.6GHz, for ultra-low power applications from IoT, M2M to 5G available from T2MIP (Thursday Oct. 29, 2020)
  T2MIP is pleased to announce the availability of a unique 3rd Generation SDR RF IP in TSMC40ULP with a contiguous frequency range from 100MHz-2.6GHz for ultra-low power IOT applications.
  
  
• Analog Bits Announces Analog IP Availability on Samsung Technologies (Wednesday Oct. 28, 2020)
  Analog Bits announced a comprehensive and differentiating foundation analog IP portfolio today on multiple Samsung Foundry technologies, including 32LP, 28LPP, 28FDSOI, 14LPP, 8LPP, 7LPP, 5LPE.
  
  
• Rambus IPsec Packet Engine Secures 5G Networking at 10 Gbps (Wednesday Oct. 28, 2020)
  Rambus today announced the availability of a high-performance IPsec Packet Engine with integrated DPDK and companion key negotiation toolkit capable of securing 5G network traffic at data rates from 1 to 10 Gbps.
  
  
• QuickLogic Announces the ArcticPro 3 eFPGA IP for Samsung 28FDS Process (Wednesday Oct. 28, 2020)
  QuickLogic today announced the availability of its ArcticPro™ 3 embedded FPGA (eFPGA) IP, which is now available on Samsung's 28nm FD–SOI process
  
  
• Micro Magic, Inc. Unleashes World's Fastest RISC-V Core (Monday Oct. 26, 2020)
  Today Micro Magic, Inc. announced the world’s fastest 64-bit RISC-V core achieving 5GHz and 13,000 CoreMarks at 1.1V. A single Micro Magic core running at 0.8V nominal delivers 11,000 CoreMarks at 4.25GHz consuming only 200mW.
  
  
• PLDA demonstrates successful PCIe 5.0 Link Training at 32 GT/s with its PCIe 5.0 controller and Broadcom PHY (Thursday Oct. 22, 2020)
  PLDA, the industry leader in PCI Express® controller IP solutions has today unveiled their PCIe 5.0 demonstration. The demo showcases stable PCIe 5.0 Link Training (32 GT/s) and exceptional signal integrity with a Broadcom® PCIe 5.0 PHY platform.
  
  
• Faraday Brings Advanced Audio ASIC Solutions to the Music Entertainment Industry (Wednesday Oct. 21, 2020)
  Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today announced gains in advanced to high-end audio applications with adoption and recognition from some of the top brands in musical instruments.
  
  
• TSMC 12FFC silicon proven SERDES Phy IPs' for HDMI 2.1, PCIe Gen5, DDR4, USB 4 & MIPI Interfaces available immediately for your next SoC (Tuesday Oct. 20, 2020)
  T2M, the global independent semiconductor IP Cores & Technology provider, is pleased to announce the availability of a comprehensive range of Silicon Proven SERDES Phy IPs in TSMC’s advance 12FFC process technology.
  
  
• Latest NPU adds to Arm's AI Platform performance, applicability, and efficiency (Monday Oct. 19, 2020)
  With an ever-increasing range of devices adding artificial intelligence (AI) functionality, Arm today announced the latest member of its Ethos product line, the Arm Ethos-U65 microNPU (Neural Processing Unit).
  
  
• CSEM joins forces with GLOBALFOUNDRIES to deliver best-in-class Bluetooth Dual-Mode silicon IP for next generation portable audio (Thursday Oct. 15, 2020)
  CSEM, a leader in ultra-low-power RF design, announced today at the GLOBALFOUNDRIES® (GF®) Global Technology Conference (GTC) EMEA that CSEM has released its Bluetooth Dual-Mode silicon IP on GF’s 22nm FD-SOI (22FDX®) platform for next generation of portable audio devices.
  
  
• Synopsys Demonstrates Industry's First PCI Express 5.0 IP Interoperability with Intel's Future Xeon Scalable Processor (Tuesday Oct. 13, 2020)
  Synopsys today announced its collaboration with Intel to achieve successful system-level interoperability between the Synopsys DesignWare Controller and PHY IP for PCI Express 5.0 and future Intel Xeon Scalable processors (codename Sapphire Rapids).
  
  
• Innosilicon Achieves World-First Tapeout Success on SMIC N+1 Process (Tuesday Oct. 13, 2020)
  Innosilicon, as a global one-stop provider of IP and ASIC customization, has achieved the world-first tapeout success on the advanced SMIC FinFET N+1 process with all the function tests passed in one stroke. This marks a significant milestone of the process iterations and joint efforts in the past few months.
  
  
• Imagination launches IMG B-Series: Doing more with multi-core (Tuesday Oct. 13, 2020)
  Imagination Technologies announces IMG B-Series, a new expanded range of GPU IP. With its advanced multi-core architecture, B-series enables Imagination customers to reduce power while reaching higher levels of performance than any other GPU IP on the market.
  
  
• Synopsys DesignWare CXL IP Supports AMBA CXS Protocol Targeting High-Performance Computing SoCs (Thursday Oct. 08, 2020)
  Synopsys today announced that its DesignWare® CXL Controller IP now supports the AMBA® CXS protocol, enabling an efficient interface with the latest, highly scalable Arm® Neoverse™ Coherent Mesh Network to provide an optimized multichip IP stack for a range of high-performance computing, datacenter, and networking system-on-chip (SoCs).
  
  
• Pushing the boundaries of performance and security to unleash the power of 64-bit computing (Thursday Oct. 08, 2020)
  Arm highlights its next two generations of CPUs, codenamed Matterhorn and Makalu, with up to a 30% performance uplift
  
  
• Think Silicon to introduce a new Inference Micro GPU Architecture based on RISC-V at Linley Fall Virtual Processor Conference (Thursday Oct. 08, 2020)
  Think Silicon extended its IP portfolio with a new inference Micro GPU Architecture based on RISC-V ISA suitable for AI-Vision and graphics tasks to enable different classes of performance, efficiency, and features for application and deeply embedded uses.
  
  
• Cadence Announces Complete DDR5/LPDDR5 IP Solution for TSMC N5 Process Technology (Thursday Oct. 08, 2020)
  Cadence today announced the immediate availability of a complete, silicon-proven Cadence® IP supporting the DDR5 and LPDDR5 DRAM memory standards on TSMC N5 process.
  
  
• Attopsemi's I-fuse Memory Solution Now Qualified and Available on X-FAB's 130nm RF-SOI Technology (Thursday Oct. 08, 2020)
  X-FAB Silicon Foundries, the leading analog/mixed-signal and specialty foundry, together with Attopsemi, innovator of I-fuse™ one-time programmable (OTP) IP solutions, have entered into a collaboration to satisfy the memory requirements of 5G technology.
  
  
• CAST Introduces Ultra-Low Latency TSN Ethernet Switch IP Core (Wednesday Oct. 07, 2020)
  Today at the virtual TSN/A Technology and Applications Conference, silicon intellectual property provider CAST, Inc. announced a new IP core that implements a switch for Time-Sensitive Networking (TSN) Ethernet networks as increasingly used in automotive, industrial, medical, and other systems.
  
  
• VSORA Introduces Small Footprint, Low-Power PetaFLOPS Platform Enabling L4/L5 Autonomous Driving (Wednesday Oct. 07, 2020)
  VSORA, a provider of high-performance silicon intellectual property (IP) solutions for artificial intelligence, digital communications and advanced driver-assistance systems (ADAS) applications, today unveiled the first PetaFLOPS computational platform to accelerate Level 4 (L4) and Level 5 (L5) autonomous vehicles designs.
  
  
• OpenFive and AnalogX to Provide Optimized Chip-to-Chip Interface IP Solutions (Monday Oct. 05, 2020)
  Interlaken C2C Controller IP from OpenFive and AXLinkIO SerDes IP from AnalogX achieves ultra-low latency and <1pJ/bit solution for a Tier-1 customer
  
  
• Synopsys Delivers Industry's First Processor IP Certified for Full ISO 26262 ASIL D Compliance (Wednesday Sep. 30, 2020)
  Synopsys, Inc. (Nasdaq: SNPS) today announced that the DesignWare® ARC® EM22FS Functional Safety Processor has achieved certification for full ISO 26262 automotive safety integrity level (ASIL) D compliance, meeting both random hardware fault detection and systematic functional safety development flow requirements.
  
  
• Fraunhofer IPMS develops TSN Switch IP Core (Wednesday Sep. 30, 2020)
  Time Sensitive Networking (TSN) is an extension of the IEEE 802.1 standard and aims to create reliable, deterministic and convergent Ethernet networks. The Fraunhofer IPMS now completes its TSN IP Core family with a TSN Switch IP Core and will present the innovation at the TSN/A Conference from October 7-8, 2020.
  
  
• New Arm technologies enable safety-capable computing solutions for an autonomous future (Tuesday Sep. 29, 2020)
  The new suite of IP includes the Arm® Cortex®-A78AE CPU, Arm Mali™-G78AE GPU, and Arm Mali-C71AE ISP, engineered to work together in combination with supporting software, tools and system IP to enable silicon providers and OEMs to design for autonomous workloads.
  
  
• Cadence Announces Broad IP Collaboration with GLOBALFOUNDRIES on 12LP/12LP+ Solutions (Monday Sep. 28, 2020)
  Cadencetoday announced broad IP collaboration with GLOBALFOUNDRIES® (GF®) on the 12LP platform and 12LP+ solution encompassing support for advanced memory interfaces including DDR4, DDR5, GDDR6, LPDDR4X and LPDDR5, as well as chiplet-based PHY IP and Cadence’s flagship 16G multi-protocol SerDes.
  
  
• Synopsys and GLOBALFOUNDRIES Collaborate to Develop Broad Portfolio of DesignWare IP for 12LP+ FinFET Solution (Thursday Sep. 24, 2020)
  Synopsys, Inc. (Nasdaq: SNPS) today announced its collaboration with GLOBALFOUNDRIES® (GF®) to develop a broad portfolio of DesignWare® IP for GF's 12LP+ FinFET solution, including USB4/3.2/DPTX/3.0/2.0, PCIe 5.0/4.0/2.1, die-to-die HBI and 112G USR/XSR, 112G Ethernet, DDR5/4, LPDDR5/4/4X, MIPI M-PHY, Analog-to-Digital Converter, and one-time programmable (OTP) non-volatile memory (NVM) IP.
  
  
• Vidatronic Launches New 22 nm Analog IP For Ultra-Low-Power, System-On-Chip Physical Attack Mitigation In Internet Of Things (IoT) Applications (Thursday Sep. 24, 2020)
  Vidatronic today announced an addition to its low-power analog IP portfolio, the 22 nm Series for integration into application-specific integrated circuits (ASICs) and systems on a chip (SoCs).
  
  
• Analog Bits Announces Foundation Analog IP Availability on GLOBALFOUNDRIES 12LP FinFET Platform (Thursday Sep. 24, 2020)
  Analog Bits today announced a comprehensive library of foundation analog IP portfolio that is available on GLOBALFOUNDRIES® (GF®) 12LP FinFET platform and 12LP+ solution for artificial intelligence (AI), cloud computing, and high-end consumer system-on-chips (SoCs).
  
  
• BrainChip Confirms Validation of the Akida Neural Processor (Thursday Sep. 24, 2020)
  BrainChip Holdings Ltd (ASX: BRN), a leading provider of ultra-low power high performance AI technology, today announced that the Company has validated the Akida Neuromorphic System-on-Chip (NSoC) design with functional silicon.