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IP / SOC Products News

• eMemory and UMC Qualify NeoFuse IP on the Foundry's 28nm High Voltage Process (Monday Jan. 20, 2020)
  eMemory, the leading provider of non-volatile memory intellectual property, and United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) ("UMC"), a leading global semiconductor foundry, today announced that eMemory’s NeoFuse IP has been qualified on UMC’s 28nm High Voltage (HV) platform to target the fast-growing OLED market.
  
  
• CAST Adds Switched TSN Endpoint Controller to Time-Sensitive Networking Ethernet IP Cores Family (Friday Jan. 17, 2020)
  CAST, Inc. today announced the availability of a new IP core implementing a switched endpoint controller supporting the Time-Sensitive Networking (TSN) Ethernet standards.
  
  
• PLDA Announces Successful PCIe 4.0 Technology Compliance for its XpressRICH-AXI Controller IP (Monday Jan. 13, 2020)
  PLDA, the industry leader in PCI Express® (PCIe®) IP and data interconnect solutions, today announced that their XpressRICH-AXI™ PCIe Controller IP passed all Gold and Interoperability tests at the PCI-SIG® Compliance Workshop, held in December 2019 in Burlingame, CA.
  
  
• CSEM Bluetooth 5.1 IP icyTRX is ready for LE Audio on multiple processes (Friday Jan. 10, 2020)
  January 2020 marks the beginning of a new era for wireless audio, with the arrival of audio streaming over Bluetooth Low Energy (LE Audio), as announced this week by the Bluetooth SIG (Special Interest Group). CSEM anticipated this new feature in the latest iterations of its silicon-proven icyTRX Bluetooth LE IP, which is already fully compatible
  
  
• Synopsys Releases Industry's First Bluetooth LE Audio Codec for Power-Sensitive Audio and Voice Applications (Tuesday Jan. 07, 2020)
  New Low-Power Codec Optimized for Synopsys' ARC Processor IP Enables High-Quality Audio and Voice Streaming from Smart Home, Mobile, and Wearable Devices
  
  
• SHA IP Core with native SHA2-256 HMAC support (Tuesday Jan. 07, 2020)
  DCD, IP Core provider and SoC design house from Poland, introduced its latest DSHA2-256 IP Core, which is a universal solution which efficiently accelerates SHA2-256 hash with native HMAC mode.
  
  
• CEVA Speeds the Development of True Wireless Stereo Earbuds with its Support of Bluetooth LE Audio (Tuesday Jan. 07, 2020)
  CEVA today announced that it has enhanced its offerings for developers of true wireless stereo (TWS) earbuds and other wireless audio devices with the general release of the RivieraWaves Bluetooth Low Energy and Dual Mode IPs with support for LE Audio.
  
  
• CEVA Debuts SenslinQ Platform to Streamline Development of Contextually Aware IoT Devices (Monday Jan. 06, 2020)
  CEVA today unveiled SenslinQ™, its first integrated hardware IP and software platform that aggregates sensor fusion, sound and connectivity technologies to enable contextually aware IoT devices.
  
  
• AImotive's latest aiWare3P delivers superior NN acceleration for production L2-L3 automotive AI (Monday Dec. 30, 2019)
  AImotive, one of the world's leading suppliers of modular automated driving technologies, announced that it has begun shipment of the latest release of its acclaimed aiWare3 NN (Neural Network) hardware inference engine IP.
  
  
• Digital Blocks extends leadership of UDP/IP networking with 50 & 100 GbE (Monday Dec. 30, 2019)
  Digital Blocks extends its leadership of low-latency, high performance UDP/IP networking Verilog Cores with releases for 50 & 100 GbE networks.
  
  
• Faraday Unveils New IoT SoC Platform to Accelerate Early-Stage ASIC Development (Thursday Dec. 19, 2019)
  Faraday Technology today introduced the Faraday FIE3240 FPGA platform, the latest addition to its SoCreative!™ IoT SoC platform series. The reprogrammable FIE3240 platform offers enhanced flexibility and scalability for today’s AIoT SoC designs utilizing Arm® Cortex®-M series processors.
  
  
• Mobiveil's PCI Express 4.0 Endpoint Controller Passes PCI-SIG Gold and Interoperability Testing (Tuesday Dec. 17, 2019)
  Mobiveil, Inc., a fast-growing supplier of silicon intellectual property (SIP), platforms and IP-enabled design services, today announced that its GPEX™ PCI Express® (PCIe®) 4.0 Endpoint Controller passed PCI-SIG® Gold and Interoperability testing.
  
  
• Alma Technologies Announces Availability of a New Ultra-High Throughput JPEG 2000 Encoder IP Core (Monday Dec. 16, 2019)
  This new scalable UHT JPEG 2000 encoder IP core provides the extreme performance needed by modern video compression applications that have to cope with massive pixel rates and resolutions.
  
  
• How to multiply by 18 battery autonomy of voice control devices? (Monday Dec. 16, 2019)
  Dolphin Design have launched a breakthrough VAD semiconductor IP - the WhisperTrigger-a. This solution achieves outstanding energy efficiency and very high accuracy, thus opening the path to a new generation of always-on sensing devices.
  
  
• All M31 Automotive IP Products Received ISO 26262 Certifications (Thursday Dec. 12, 2019)
  Technology Corporation (Taiwan stock code: 6643), a professional silicon Intellectual Property (IP) provider, announced today of their “PCIe PHY” and “MIPI D PHY” ISO 26262 Automotive Safety Integrity Level ASIL B Ready certification approved by German authority SGS-TÜV.
  
  
• Cobham Releases RISC-V Processor IP Core (Wednesday Dec. 11, 2019)
  Cobham Gaisler announced today that it will release a new line of processor Intellectual Property (IP) cores that implements the RISC-V instruction set architecture (ISA). The NOEL-V processor IP core, the first product in the family, will be made available on 25 December for download into Xilinx’ Kintex UltraSCALE FPGAs.
  
  
• Cobham Releases LEON5 Processor IP Core (Wednesday Dec. 11, 2019)
  The new LEON5 IP core implements the SPARC V8 32-bit ISA, a 32-bit architecture. LEON5 is a super-scalar dual-issue processor that provides software backward compatibility with previous generation LEON processors while increasing performance both in terms of maximum achievable operating frequency and amount of computations performed per system clock cycle.
  
  
• AccelerComm Reduces 5G Latency by up to 16x with NR LDPC Channel Coding (Wednesday Dec. 11, 2019)
  AccelerComm announced today the launch and general availability of the 5G NR LDPC version of its error correction IP, which reduces latency up to 16x to support numerology 4 in 3GPP 38.211 and also results in significant power savings for mobile networks with lower order numerology networks.
  
  
• SiFive Announces New Technologies for Mission-Critical and AI Markets (Wednesday Dec. 11, 2019)
  New SiFive Apex cores for mission-critical markets and SiFive Intelligence cores for vector processing workloads create a comprehensive IP portfolio for high-growth markets
  
  
• Codasip Teams Up with Western Digital to Support Adoption of Open-Source Processors (Tuesday Dec. 10, 2019)
  Codasip announced today that it has joined forces with Western Digital Corp. to become the preferred provider of hardware implementation packages and expert technical support for users of Western Digital’s SweRV Core EH1, a RISC-V core currently available to the open-source community and further supported by the open-source development organization CHIPS Alliance.
  
  
• Creonic Continues to Extend its Leading SATCOM IP Core Portfolio (Tuesday Dec. 10, 2019)
  Creonic GmbH, a leading IP core provider in the communications market, announced updates and improvements today, as well as new IP cores for satellite communications (SATCOM). The extensions complement the company’s SATCOM IP core portfolio, the broadest in the market.
  
  
• UltraSoC donates RISC-V trace implementation to enable true open-source development (Monday Dec. 09, 2019)
  UltraSoC today announced it will offer an open-source implementation of its industry-leading RISC-V trace encoder via the OpenHW Group.
  
  
• Andes 45-Series Expands RISC-V High-end Processors 8-Stage Superscalar Processor Balances High Performance, Power Efficiency, and Real-time Determinism with Rich RISC-V Ecosystem (Thursday Dec. 05, 2019)
  Andes Technology announces AndesCore™ 45-series CPU cores today. It is equipped with efficient superscalar pipeline to address a wide range of high-performance, power-sensitive and real-time embedded systems such as 5G, In-Vehicle Infotainment (IVI), Advanced Driver Assistance Systems (ADAS) and Solid State Disks (SSD).
  
  
• Mixel Announces Immediate Availability of MIPI D-PHY v2.5 IP (Tuesday Dec. 03, 2019)
  Mixel®, a leading provider of mixed-signal intellectual property (IP), announced today that its MIPI® D-PHY IP compliant to MIPI D-PHY v2.5 specification is now available. MIPI D-PHY supports MIPI Camera Serial Interface 2 (CSI-2), as well as Display Serial Interface (DSISM) and DSI-2.
  
  
• Think Silicon demonstrates early preview of Industry's first RISC-V ISA based 3D GPU at the RISC-V Summit (Tuesday Dec. 03, 2019)
  Think Silicon, recognized for the successful ultra-low power NEMA® GPU-Series for MCU driven SoCs, announced the demonstration of the industry’s first RISC-V ISA based 3D GPU -- the NEOX|V™.
  
  
• Imagination launches IMG A-Series: "The GPU of Everything" (Tuesday Dec. 03, 2019)
  Imagination Technologies announces the tenth generation of its PowerVR graphics architecture, the IMG A-Series. The fastest GPU IP ever released, IMG A-Series evolves the PowerVR GPU architecture to fulfil the graphics and compute needs of the full spectrum of next-generation devices.
  
  
• Silex Insight Introduces Video Codec IP using RAW input (CFA) (Tuesday Nov. 26, 2019)
  Silex Insight, a leading provider of video codec & AV over IP solutions, announces the extension of its codec family by introducing Video Codec IP (JPEG 2000/VC-2 HQ) using RAW input­ from Bayer filter (CFA).
  
  
• High-speed comms options enable in-life debug and optimization for datacenter, HPC and storage customers (Tuesday Nov. 19, 2019)
  UltraSoC today announced new high-speed communications capabilities within its embedded analytics architecture, supporting debug and performance optimization in datacenters, high-performance computing, AI and storage applications.
  
  
• Faraday and UMC Collaborate to Launch a Complete Set of 22nm Fundamental IP (Monday Nov. 18, 2019)
  Faraday Technology and United Microelectronics today announced the availability of Faraday's fundamental IP on UMC's 22nm ultra-low-power (ULP) and ultra-low-leakage (ULL) processes. The silicon-proven 22ULP/ULL fundamental IP, including multi-Vt standard cell libraries, ECO libraries, IO libraries, PowerSlash™ kit, and memory compilers, offers significant power reduction for the next level of SoC design.
  
  
• New Cadence UltraLink D2D PHY IP for Die-to-Die Connectivity Enables High-Performance Applications with Cost-Effective Packaging (Wednesday Nov. 13, 2019)
  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Cadence® UltraLink™ D2D PHY IP, a high-performance, low-latency PHY for die-to-die connectivity targeted at the AI/ML, 5G, cloud computing and networking market segments.