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IP / SOC Products News

• SmartDV Offers New Design IP for DDR5 and LPDDR5 (Tuesday Feb. 18, 2020)
  SmartDV™ Technologies today introduced its new Design IP for DDR5 and LPDDR5 SDRAM controllers. The fast, efficient DDR5 and LPDDR5 Design IP offers low power and latency, reduced gate count for increased memory interface bandwidth, and fully supports the latest DDR5 and LPDDR5 specifications.
  
  
• Synopsys Launches New ARC Communications IP Subsystem for Wireless Narrowband IoT Designs (Thursday Feb. 13, 2020)
  Integrated Hardware and Software IP Subsystem Delivers Efficient 3GPP Release 14-Compliant Communications for Machine to Machine, Smart Cities, and Industrial Automation Applications
  
  
• Socionext Introduces Time-Sensitive Network (TSN) IP to Realize Smart Factories (Thursday Feb. 13, 2020)
  Socionext Inc. has developed a Time-Sensitive Network (TSN) IP for FPGA and ASIC implementation. The IP, which provides true deterministic Ethernet for industrial applications, is compliant with the next-generation Ethernet TSN (communication standard IEEE 802.1 Subset) and its evaluation environment.
  
  
• New Mathematically Lossless Video Compression IP Cores Announced by Hardent (Wednesday Feb. 12, 2020)
  Hardent today announced the forthcoming availability of its new mathematically lossless video compression IP cores. Hardent’s lossless video compression (HLVC) technology offers mathematically lossless compression specifically designed to facilitate the challenges associated with capturing, processing, storing, and playing back large amounts of raw data from automotive image sensors.
  
  
• SmartDV Adds Support for MIPI I3C 1.1 Across Entire IP Portfolio (Wednesday Feb. 12, 2020)
  SmartDV™ Technologies today announced its entire IP portfolio supports the new MIPI I3C® v1.1 utility and control bus specification designed to simplify integration and improve cost efficiencies for development of smartphone, wearable, high-performance server and automotive applications.
  
  
• Low-Latency Ethernet MAC IP Core from CAST now ASIL-D Certified (Tuesday Feb. 11, 2020)
  Semiconductor intellectual property (IP) provider CAST, Inc. today announced that the Low-Latency Ethernet Media Access Controller IP core it offers is now certified to conform to the ISO-26262 safety standard and is available ASIL-D ready.
  
  
• New AI technology from Arm delivers unprecedented on-device intelligence for IoT (Monday Feb. 10, 2020)
  Today, Arm announced significant additions to its artificial intelligence (AI) platform, including new machine learning (ML) IP, the Arm® Cortex®-M55 processor and Arm Ethos™-U55 NPU, the industry’s first microNPU (Neural Processing Unit) for Cortex-M, designed to deliver a combined 480x leap in ML performance to microcontrollers.
  
  
• Chips&Media Pioneering With The World's First Real-time Multi-Standard Decoder, including AV1, HW IP, WAVE517 (Monday Feb. 03, 2020)
  Chips&Media, today announced the pre-release of multi-standard HW IP named WAVE517, targeting 4K Ultra-High-Definition (UHD), which is the first in the industry to support almost every codec standards for the UHD in the market, including the next-generation AV1 standard.
  
  
• Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with targeted applications in DMA Streaming of Video and Data over PCIe or UDP/IP Network Interface. (Thursday Jan. 30, 2020)
  Digital Blocks announces additions to DMA Controller Verilog IP Core offerings with capabilites to stream video or data to and from memory as well as to and from over PCIe and UDP/IP Network Interfaces.
  
  
• Flex Logix EFLX 1K eFPGA Core Design Kits Available Now For TSMC 40nm ULP And 40nm LP Process Technologies (Monday Jan. 27, 2020)
  Flex Logix Technologies, Inc., the leading supplier of embedded FPGA (eFPGA) IP, architecture and software, announced today a new EFLX eFPGA core optimized for the needs of customers on TSMC 40nm Ultra Low Power (ULP) and 40nm Low Power (LP) process technologies.
  
  
• sureCore Opens Low Power Memory Compiler Access (Tuesday Jan. 21, 2020)
  sureCore Limited is opening its low power memory compiler for 30 days to qualifying companies to evaluate the capabilities of their PowerMiser and EverOn standard SRAM IP products on low power metrics. The new service will prove particularly useful for constraint and compute intensive SoC designs.
  
  
• eMemory and UMC Qualify NeoFuse IP on the Foundry's 28nm High Voltage Process (Monday Jan. 20, 2020)
  eMemory, the leading provider of non-volatile memory intellectual property, and United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) ("UMC"), a leading global semiconductor foundry, today announced that eMemory’s NeoFuse IP has been qualified on UMC’s 28nm High Voltage (HV) platform to target the fast-growing OLED market.
  
  
• CAST Adds Switched TSN Endpoint Controller to Time-Sensitive Networking Ethernet IP Cores Family (Friday Jan. 17, 2020)
  CAST, Inc. today announced the availability of a new IP core implementing a switched endpoint controller supporting the Time-Sensitive Networking (TSN) Ethernet standards.
  
  
• PLDA Announces Successful PCIe 4.0 Technology Compliance for its XpressRICH-AXI Controller IP (Monday Jan. 13, 2020)
  PLDA, the industry leader in PCI Express® (PCIe®) IP and data interconnect solutions, today announced that their XpressRICH-AXI™ PCIe Controller IP passed all Gold and Interoperability tests at the PCI-SIG® Compliance Workshop, held in December 2019 in Burlingame, CA.
  
  
• CSEM Bluetooth 5.1 IP icyTRX is ready for LE Audio on multiple processes (Friday Jan. 10, 2020)
  January 2020 marks the beginning of a new era for wireless audio, with the arrival of audio streaming over Bluetooth Low Energy (LE Audio), as announced this week by the Bluetooth SIG (Special Interest Group). CSEM anticipated this new feature in the latest iterations of its silicon-proven icyTRX Bluetooth LE IP, which is already fully compatible
  
  
• Synopsys Releases Industry's First Bluetooth LE Audio Codec for Power-Sensitive Audio and Voice Applications (Tuesday Jan. 07, 2020)
  New Low-Power Codec Optimized for Synopsys' ARC Processor IP Enables High-Quality Audio and Voice Streaming from Smart Home, Mobile, and Wearable Devices
  
  
• SHA IP Core with native SHA2-256 HMAC support (Tuesday Jan. 07, 2020)
  DCD, IP Core provider and SoC design house from Poland, introduced its latest DSHA2-256 IP Core, which is a universal solution which efficiently accelerates SHA2-256 hash with native HMAC mode.
  
  
• CEVA Speeds the Development of True Wireless Stereo Earbuds with its Support of Bluetooth LE Audio (Tuesday Jan. 07, 2020)
  CEVA today announced that it has enhanced its offerings for developers of true wireless stereo (TWS) earbuds and other wireless audio devices with the general release of the RivieraWaves Bluetooth Low Energy and Dual Mode IPs with support for LE Audio.
  
  
• CEVA Debuts SenslinQ Platform to Streamline Development of Contextually Aware IoT Devices (Monday Jan. 06, 2020)
  CEVA today unveiled SenslinQ™, its first integrated hardware IP and software platform that aggregates sensor fusion, sound and connectivity technologies to enable contextually aware IoT devices.
  
  
• AImotive's latest aiWare3P delivers superior NN acceleration for production L2-L3 automotive AI (Monday Dec. 30, 2019)
  AImotive, one of the world's leading suppliers of modular automated driving technologies, announced that it has begun shipment of the latest release of its acclaimed aiWare3 NN (Neural Network) hardware inference engine IP.
  
  
• Digital Blocks extends leadership of UDP/IP networking with 50 & 100 GbE (Monday Dec. 30, 2019)
  Digital Blocks extends its leadership of low-latency, high performance UDP/IP networking Verilog Cores with releases for 50 & 100 GbE networks.
  
  
• Faraday Unveils New IoT SoC Platform to Accelerate Early-Stage ASIC Development (Thursday Dec. 19, 2019)
  Faraday Technology today introduced the Faraday FIE3240 FPGA platform, the latest addition to its SoCreative!™ IoT SoC platform series. The reprogrammable FIE3240 platform offers enhanced flexibility and scalability for today’s AIoT SoC designs utilizing Arm® Cortex®-M series processors.
  
  
• Mobiveil's PCI Express 4.0 Endpoint Controller Passes PCI-SIG Gold and Interoperability Testing (Tuesday Dec. 17, 2019)
  Mobiveil, Inc., a fast-growing supplier of silicon intellectual property (SIP), platforms and IP-enabled design services, today announced that its GPEX™ PCI Express® (PCIe®) 4.0 Endpoint Controller passed PCI-SIG® Gold and Interoperability testing.
  
  
• Alma Technologies Announces Availability of a New Ultra-High Throughput JPEG 2000 Encoder IP Core (Monday Dec. 16, 2019)
  This new scalable UHT JPEG 2000 encoder IP core provides the extreme performance needed by modern video compression applications that have to cope with massive pixel rates and resolutions.
  
  
• How to multiply by 18 battery autonomy of voice control devices? (Monday Dec. 16, 2019)
  Dolphin Design have launched a breakthrough VAD semiconductor IP - the WhisperTrigger-a. This solution achieves outstanding energy efficiency and very high accuracy, thus opening the path to a new generation of always-on sensing devices.
  
  
• All M31 Automotive IP Products Received ISO 26262 Certifications (Thursday Dec. 12, 2019)
  Technology Corporation (Taiwan stock code: 6643), a professional silicon Intellectual Property (IP) provider, announced today of their “PCIe PHY” and “MIPI D PHY” ISO 26262 Automotive Safety Integrity Level ASIL B Ready certification approved by German authority SGS-TÜV.
  
  
• Cobham Releases RISC-V Processor IP Core (Wednesday Dec. 11, 2019)
  Cobham Gaisler announced today that it will release a new line of processor Intellectual Property (IP) cores that implements the RISC-V instruction set architecture (ISA). The NOEL-V processor IP core, the first product in the family, will be made available on 25 December for download into Xilinx’ Kintex UltraSCALE FPGAs.
  
  
• Cobham Releases LEON5 Processor IP Core (Wednesday Dec. 11, 2019)
  The new LEON5 IP core implements the SPARC V8 32-bit ISA, a 32-bit architecture. LEON5 is a super-scalar dual-issue processor that provides software backward compatibility with previous generation LEON processors while increasing performance both in terms of maximum achievable operating frequency and amount of computations performed per system clock cycle.
  
  
• AccelerComm Reduces 5G Latency by up to 16x with NR LDPC Channel Coding (Wednesday Dec. 11, 2019)
  AccelerComm announced today the launch and general availability of the 5G NR LDPC version of its error correction IP, which reduces latency up to 16x to support numerology 4 in 3GPP 38.211 and also results in significant power savings for mobile networks with lower order numerology networks.
  
  
• SiFive Announces New Technologies for Mission-Critical and AI Markets (Wednesday Dec. 11, 2019)
  New SiFive Apex cores for mission-critical markets and SiFive Intelligence cores for vector processing workloads create a comprehensive IP portfolio for high-growth markets