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IP / SOC Products News

• Chips&Media launches HEVC/H.264 combined codec IP (Single Core) optimized for UHD (4K, 60 FPS) (Wednesday Jun. 13, 2018)
  Chips&Media, Inc. a leading video IP company headquartered in Seoul, Korea, announced the introduction of WAVE521C, a new codec IP with single core based integrated HEVC and H.264.
  
  
• CAST Adds JPEG-LS Decoder to Lossless Image Compression IP Core Suite (Tuesday Jun. 12, 2018)
  Semiconductor intellectual property provider CAST, Inc. has released a JPEG-LS Decoder IP core that—together with the JPEG-LS Encoder already available—provides an efficient hardware compression solution for the lossless or near-lossless transmission or storage of high quality images or video sequences.
  
  
• MIPS I6500-F First High Performance 64 Bit Multi-Cluster CPU IP to Receive ISO 26262 and LEC 61508 Certification (Monday Jun. 11, 2018)
  MIPS today announced that its I6500-F CPU IP core, designed as a Safety Element out of Context (SEooC), is the first high performance 64 bit multi-cluster CPU IP to receive formal certification of compliance for ASIL B [D], based on ISO 26262: 1st edition 2011 (&DIS 2nd Edition 2018) and IEC 61508 SIL 2.
  
  
• PowerVR Series2NX neural network accelerator cores set the standard for performance and cost-efficiency (Friday Jun. 08, 2018)
  Imagination Technologies announces two neural network cores, the AX2185 and AX2145, designed to enable high-performance computation of neural networks at very low power consumption in minimal silicon area.
  
  
• Arteris IP Announces CodaCache Standalone Last Level Cache (Thursday Jun. 07, 2018)
  Arteris IP today announced the CodaCache standalone last level cache (LLC) for high-performance systems-on-chip (SoCs). The Arteris IP CodaCache LLC is highly configurable and offers system-wide performance improvements and power savings while providing seamless integration into SoCs with Arm® AMBA® AXI interfaces.
  
  
• Mobiveil and Avery Design Systems Partner to Provide SoC Designers a Fully Verified and Compliant PCIe 5.0 IP Solution (Wednesday Jun. 06, 2018)
  Mobiveil, Inc. today announced that it is partnering with Avery Design Systems to deliver a complete PCIe 5.0 IP solution for SoC designers needing a fully verified and compliant PCIe 5.0 interface solution for their designs.
  
  
• eSilicon revolutionizes machine learning ASIC platform (MLAP) market (Tuesday Jun. 05, 2018)
  eSilicon announced today at the Machine Learning and AI Developer’s Conference a fundamentally new approach to building application-specific integrated circuits (ASICs) for artificial intelligence (AI)/neural network applications called the neuASIC platform.
  
  
• IP Cores, Inc. Announces Modifications of the 400 Gbps MACsec IP Cores (Monday Jun. 04, 2018)
  IP Cores, Inc., (California, USA, http://www.ipcores.com) has announced modifications of its MSP10-512 cores that support line-speed MACsec encryption and decryption for the 400 Gbps Ethernet.
  
  
• PLDA Announces Availability of XpressRICH5 PCIe 5.0 Controller IP (Monday Jun. 04, 2018)
  PLDA today announced availability of their XpressRICH5™ PCIe® 5.0 Controller IP. PLDA’s XpressRICH5 supports rev. 0.7 of the PCIe 5.0 Specification and is available for ASIC, SoC and FPGA implementation, allowing early adopters to seamlessly improve their link throughtput to 32 GT/s per lane and reduce their overall latency.
  
  
• Arm announces new suite of IP for premium mobile experiences (Friday Jun. 01, 2018)
  For Small Screens to Large: Introducing a New Suite of IP for Premium Mobile Experiences
  
  
• Imec demonstrates compatibility of state-of-the-art 0.8V-transceiver, with industry standard Arm Cordio IP for BLE 5 (Wednesday May. 30, 2018)
  The radio combines imec’s latest transceiver frontend, operating from a nominal supply as low as 0.8V, with Arm’s qualified and silicon-proven Cordio® Bluetooth low energy 5 digital baseband. Designed for IoT applications demanding very low power consumption, such as leave-behind sensors or wearables, the solution demonstrates industry compatibility of these novel, highly energy-efficient radios.
  
  
• IP Cores, Inc. Announces Additional Shipments of its Reed-Solomon Codec for 400G Ethernet (Tuesday May. 29, 2018)
  IP Cores, Inc. announces additional shipments of RS (528,514) and RS (544,514) forward error correction (FEC) codecs for the IEEE 200 Gbps and 400 Gbps IEEE Ethernet standards.
  
  
• Dolphin Integration announces the availability of its RISC-V subsystem: RV32 Tornado (Monday May. 28, 2018)
  Dolphin Integration announces the availability of its RISC-V subsystem called RV32 Tornado. This MCU subsystem has been designed to fit the IoT requirements in terms of area and low-power consumption.
  
  
• Kandou Announces Availability of Glasswing USR SerDes IP (Monday May. 28, 2018)
  Kandou Bus today announced the introduction of the Glasswing™ USR SerDes, enabling the assembly of multiple chiplets inside a shared package without the need for costly silicon interposers
  
  
• IP Cores, Inc. Announces Shipment of a 32-bit Version of its Ultra Low Power FFT IP Core (Wednesday May. 23, 2018)
  IP Cores, Inc., California, USA has announced shipment of a 32-bit core from its popular low-power FFT core family, FFT1.
  
  
• Arasan and Test Evolution announce Industry's first C-PHY / D-PHY Combo Compliance Analyzer with Arasan's Total MIPI IP Solution (Wednesday May. 23, 2018)
  Arasan Chip Systems is proud to announce the immediate availability of Test Evolution IP110 series C-PHY / D-PHY Combo protocol analyzers built using Arasan’s Total MIPI IP Solutions including C-PHY / D-PHY Combo IP cores.
  
  
• Chipus grows its battery charger IP family (Wednesday May. 23, 2018)
  Chipus announces the tape-out of its 3rd generation of battery charger IP with several improvements when compared with previous versions.
  
  
• Dolphin Integration introduces new Dual Port memory compilers in TSMC 40 nm (Monday May. 21, 2018)
  Dolphin Integration, leader in innovative design solutions for the next generation of energy-efficient System-on-Chips, has announced the launch of its new Dual Port RAM compiler ”ERA” in TSMC 40 nm. This cost-effective RAM compiler creates memories maximizing battery life whilst reducing silicon area.
  
  
• Synopsys Introduces Industry's First ASIL D Ready Embedded Vision Processor IP for ADAS Applications and Self-Driving Vehicles (Thursday May. 17, 2018)
  Synopsys today announced its new automotive safety integrity level (ASIL) B, C, and D Ready DesignWare® EV6x Embedded Vision Processors with Safety Enhancement Package (SEP) to accelerate the development of automotive system-on-chips (SoCs).
  
  
• New VDC-M (VESA Display Compression-M) IP Cores Launched By Hardent (Wednesday May. 16, 2018)
  Hardent, a VESA® member and leading provider of video compression IP cores, has today announced the launch of VDC-M encoder and decoder IP cores supporting the new VESA Display Compression-M standard.
  
  
• NetSpeed Furthers Leadership in Industrial, Factory Automation and Safety-critical Flight Systems with IEC 61508 Certification (Tuesday May. 15, 2018)
  NetSpeed Systems, Inc. today announced that its interconnect IP portfolio is now certified for the IEC 61508 functional safety standard. SGS-TÜV Saar GmbH, an independent accredited assessor, certified the IP in accordance with IEC 61508 Safety Integrity Level 3 (SIL3), the highest level possible for an IP-only component.
  
  
• MagnaChip and YMC to Offer Cost Effective 0.13 micron Multiple-Time Programmable (MTP) IP Solutions (Monday May. 14, 2018)
  MagnaChip Semiconductor Corporation (MagnaChip Semiconductor) (NYSE: MX), a designer and manufacturer of analog and mixed-signal semiconductor products, announced today the availability of 0.13 micron Multiple-Time Programmable Intellectual Property (MTP-IP) memory cores targeted for mobile and industrial applications.
  
  
• Crossbar ReRAM Enabling AI at the Edge (Monday May. 14, 2018)
  Crossbar, the ReRAM technology leader, today announced its ReRAM technology for artificial intelligence (AI) is available for licensing.
  
  
• Chipus concludes important milestone in the development of analog IP in SilTerra I18L technology (Thursday May. 10, 2018)
  Chipus is announcing the tape out of its Ultra-Low-Power IoT Analog IPs, targeted for SilTerra’s IoT platform, as part of the strategic partnership to provide analog IP solutions for customers.
  
  
• Arasan Announces Industries First MIPI I3C Master IP Core compliant to the I3C HCI Specifications v1.0 (Wednesday May. 09, 2018)
  Arasan Chip Systems announces the immediate availability of its MIPI I3C Host Controller Interface (“I3C HCI”) Master IP core compliant to the just released MIPI I3C HCI Specification Ver 1.0. The new I3C HCI specification standardizes the interface to enable building of common software drivers to enable easy access to the I3C HCI v1.0 Compliant Host Controllers.
  
  
• IntelliProp Announces NVMe-to-SATA Bridge IP Core (Wednesday May. 09, 2018)
  IntelliProp, Inc., a leader in innovative Intellectual Property (IP) Cores and semiconductors for Data Storage and Memory applications, announced today the release of the IPP-NV186A-BR, NVMe-to-SATA Bridge IP Core.
  
  
• NetSpeed and Northwest Logic Partner to Boost Performance in Hyperscale and Automotive SoCs (Tuesday May. 08, 2018)
  NetSpeed Systems, Inc. and Northwest Logic today announced a partnership to deliver high throughput memory subsystem solutions for customers designing SoCs for hyperscale and automotive applications.
  
  
• Silex Inside upgrades IP offering for compatibility with Chinese security standards (Tuesday May. 08, 2018)
  Silex Inside, the leading provider of IP cores for cryptography, announces that it has upgraded its hardware IP blocks for security to adhere to the SM2, SM3, and SM4 standards for secure communication defined by the Chinese authorities.
  
  
• Comcores Announce Availability of flexible eCPRI IP solution (Tuesday May. 08, 2018)
  Denmark Headquartered Comcores ApS, a fast growing specialized supplier of silicon intellectual property (SIP) today announced the availability of eCPRI 1.0 IP targeting FPGA and ASIC devices.
  
  
• StreamDSP Announces Availability of VITA 17.3 sFPDP Gen 3 IP Core (Monday May. 07, 2018)
  StreamDSP announces immediate availability of VITA 17.3 sFPDP Gen 3 IP Core. The recently approved VITA 17.3 specification, also known as Serial Front Panel Data Port (sFPDP) Gen 3, is a next-generation communications protocol designed as the successor to VITA 17.1.