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IP / SOC Products News

• New Arm IP brings intelligent, immersive experiences to mainstream markets (Wednesday Oct. 23, 2019)
  Arm is launching two new mainstream ML processors, as well as our latest Mali graphics and display processors. Together, this IP represents Arm’s ability to scale, bringing premium experiences to everyday and ultra-efficient consumer devices.
  
  
• BrainChip Awarded New Patent for Artificial Intelligence Dynamic Neural Network (Tuesday Oct. 22, 2019)
  BrainChip, a leading provider of ultra-low power, high performance edge AI technology, has been awarded a new patent for dynamic neural function libraries, a key component of its AI processing chip Akida.
  
  
• Synopsys Launches New ARC VPX DSP Processor IP for High-performance Signal Processing SoC Designs (Tuesday Oct. 22, 2019)
  Synopsys today announced the new DesignWare® ARC® VPX5 DSP and VPX5FS DSP Processor IP that is based on an extended ARCv2DSP instruction set and optimized for a broad range of high-performance signal processing applications, such as RADAR/LiDAR, sensor fusion, and baseband communications processing.
  
  
• Chips&Media Delivers The World's First Commercial AV1 Hardware Decoder IP, WAVE510A (Tuesday Oct. 22, 2019)
  Chips&Media recently announced the arrival of WAVE510A, the world’s first commercial AV1 hardware decoder IP that supports the next generation AV1 standard, an open royalty-free video coding format designed for high-quality video transmissions over the internet.
  
  
• OPENEDGES and INNOSILICON unveil advanced DDR Controller and DDR PHY integrated IP solutions (Tuesday Oct. 22, 2019)
  OPENEDGES Technology, Inc. the leading IP provider of Memory subsystem IP today announced a partnership with INNOSILICON to promote OPENEDGES DDR memory controller and INNOSILICON DDR PHY.
  
  
• Silex Insight Introduces Hardware Security Module (HSM) for Xilinx FPGA Devices (Thursday Oct. 17, 2019)
  Silex Insight, a leading provider for flexible security IP cores, announce a collaboration with Xilinx, Inc. to provide a hardware security module (HSM) for the Xilinx Zynq UltraScale+ MPSoC family, which is available as of today.
  
  
• M31 Memory Compiler and GPIO are certified with ASIL-D safety level of ISO 26262 (Thursday Oct. 17, 2019)
  M31 Technology today announced that: Following the high-speed interface IP MIPI M-PHY, Memory Compilers and GPIO IP have also been certified by the German institution SGS-TÜV for ISO 26262 automotive safety highest level ASIL-D Ready certification, to provide safe and reliable automotive electronic design solutions.
  
  
• sureCore PowerMiser Low Power SRAM IP Now on Samsung 28nm FDS Process Technology (Wednesday Oct. 16, 2019)
  sureCore Limited, a provider of low power SRAM products and custom memory design services, today announced that its PowerMiser low power SRAM IP is now available for designs targeting the Samsung 28nm FDS process.
  
  
• Imagination announces second generation IEEE 802.11n Wi-Fi IP designed for low-power applications (Tuesday Oct. 15, 2019)
  Imagination Technologies announces the launch of iEW220, Ensigma’s latest IEEE 802.11a/b/g/n 1X1 SISO Wi-Fi IP solution comprising of RF, baseband and MAC, supporting both 2.4GHz and 5GHz spectrum.
  
  
• GLOBALFOUNDRIES and Racyics GmbH Demonstrate Ultra-Low-Power Microcontroller for the Internet of Things (Thursday Oct. 10, 2019)
  GLOBALFOUNDRIES and Racyics GmbH will unveil a major breakthrough in the race to build more power-efficient IoT devices: record-breaking ultra-low-power operation of a commonly used microcontroller core for mixed-signal IoT applications, built on GF’s 22FDX® platform.
  
  
• Achronix, Cisco, Facebook, Netronome, NXP and zGlue Collaborate on Proof-of-Concept for Chiplet Solutions as Part of OCP ODSA Subproject (Thursday Oct. 10, 2019)
  Achronix, Cisco, Facebook, Netronome, NXP and zGlue shared details on the progress of their collaboration to validate technology and business opportunities for chiplet solutions.
  
  
• UltraSoC announces next-generation hardware-based cybersecurity products (Tuesday Oct. 08, 2019)
  UltraSoC today announced next-generation hardware-based cybersecurity products that can be used to detect, block and record cyber-attacks in a broad range of applications – from vehicles and factory robots to consumer devices.
  
  
• Silex Insight and Medium Inc. accelerate towards 1 million ECDSA signature verifications per second on a blockchain (Tuesday Oct. 08, 2019)
  Silex Insight, a leading provider of security IP cores, and Medium Inc., a Korean leading provider of blockchain and enterprise security solutions, have joined forces to deliver a blockchain platform with extreme high performance that can securely process more than 1 million signature verifications per second!
  
  
• Synopsys, Arm, and Samsung Foundry Enable Accelerated Development of Next-Generation Arm "Hercules" Processor on 5LPE Process (Tuesday Oct. 08, 2019)
  Synopsys, Inc. (Nasdaq: SNPS) today announced that Synopsys, Arm, and Samsung have actively collaborated on solutions to enable early adoption of the next-generation Arm®-based processor.
  
  
• CAN to TSN Gateway from CAST Bridges CAN 2.0/FD Buses with Time Sensitive Ethernet (Friday Oct. 04, 2019)
  IP core provides easy integration of up to seven CAN buses with an Ethernet network in automotive and industrial systems; will be shown at TSN/A Conference
  
  
• IP Controller Core CAN 2.0b and CAN FD of Fraunhofer IPMS certified according to ISO security standard (Thursday Oct. 03, 2019)
  Fraunhofer IPMS has certified its IP designs, CAN 2.0B and CAN FD Controller Core, for functional safety according to ISO26262:2018. System integrators can now be sure that this IP Core fulfills all criteria of the ASIL B level requirements.
  
  
• Adesto and Cadence Collaborate to Expand xSPI Ecosystem for Emerging IoT Devices (Wednesday Oct. 02, 2019)
  The Cadence® Memory Model for xSPI is the first commercially available model that allows customers to ensure optimal use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto®’s EcoXiP™ octal xSPI non-volatile memory (NVM).
  
  
• Data Compression Accelerators from CAST Now Available on Xilinx Alveo Boards (Friday Sep. 27, 2019)
  Semiconductor intellectual property (IP) provider CAST, Inc. today announced that its GZIP/ZLIB/Deflate Compression and Decompression reference designs are now available on Xilinx® Alveo™ Data Center Accelerator Cards.
  
  
• Sofics releases pre-silicon analog I/O's for high-speed SerDes for TSMC N5 process technology (Friday Sep. 27, 2019)
  Sofics bvba, a leading semiconductor integrated circuit IP provider announced that it has expanded its TakeCharge® Electrostatic Discharge (ESD) and Analog I/O portfolio with solutions for TSMC’s N5 process technology. The cells enable high speed and high frequency interfaces.
  
  
• SiFive Announces Key Enablement Of Trace And Debug (Thursday Sep. 26, 2019)
  SiFive, Inc., has announced the general availability of the latest update to SiFive Core IP and SiFive Core Designer in the Q3 2019 quarterly update. This release is specifically focused on the enablement of Trace and Debug functionality in the development of configurable SoC design.
  
  
• Synopsys and TSMC Collaborate to Develop Portfolio of DesignWare IP for TSMC 5nm FinFET Plus (N5P) Process (Thursday Sep. 26, 2019)
  Synopsys today announced a collaboration with TSMC to develop a broad portfolio of DesignWare® interface IP, logic libraries, embedded memories, and one-time programmable (OTP) non-volatile memory (NVM) IP on TSMC's 5-nanometer (nm) FinFET Plus (N5P) Process.
  
  
• Rambus Tapes Out 112G XSR SerDes PHY on Leading-edge 7nm Process (Thursday Sep. 26, 2019)
  Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced the tapeout of its 112G XSR SerDes PHY on a leading-edge 7nm process node optimized for PPA to support data center, networking, HPC, AI and ML applications.
  
  
• Analog Bits Showcases Silicon of Analog and Mixed Signal IP Products on TSMC N7 Process Targeting Automotive Grade with Split Corner Lots and PVT Characterization Results Available (Thursday Sep. 26, 2019)
  Analog Bits, an industry leading provider of low-power mixed-signal IP (Intellectual Property) solutions is demonstrating its silicon results targeting automotive grade for its analog and mixed signal IP products on TSMC's N7 process
  
  
• Synopsys Extends Portfolio of Cloud Computing IP with 112G Ethernet PHY for Hyperscale Data Center SoCs (Wednesday Sep. 25, 2019)
  Synopsys Extends Portfolio of Cloud Computing IP with 112G Ethernet PHY for Hyperscale Data Center SoCs
  
  
• Evaluation Boards Now Available for Flex Logix EFLX4K eFPGA on GLOBALFOUNDRIES' Most Advanced FinFET Platform (Wednesday Sep. 25, 2019)
  Flex Logix Technologies, Inc., the leading supplier of embedded FPGA (eFPGA) IP and software, today announced that it has received working first silicon of its validation chip for the EFLX 4K eFPGA IP cores running on GLOBALFOUNDRIES (GF) 12nm Leading-Performance (12LP) FinFET platform and newly announced 12LP+ solution.
  
  
• M31 Technology Develops Optimized IP Solutions on Multiple TSMC Specialty Processes (Wednesday Sep. 25, 2019)
  M31 Technology announced its series of developments geared to optimized IP solutions for TSMC's specialty processes. The development ultimate goal is to assist chip designers in achieving low power consumption, high performance, compact size, and place & route convenience.
  
  
• Analog Bits and Aragio Solutions Team Up with GLOBALFOUNDRIES to Deliver Automotive IP Solutions (Tuesday Sep. 24, 2019)
  GLOBALFOUNDRIES (GF), Analog Bits and Aragio Solutions (Aragio) announced today at GF’s annual Global Technology Conference (GTC) that they are collaborating to develop a portfolio of I/O libraries on GF’s 22nm FD-SOI (22FDX®) platform.
  
  
• Silicon Creations to Showcase PLL Developments on 22nm to 5nm Processes at TSMC 2019 Open Innovation Platform Ecosystem Forum (Monday Sep. 23, 2019)
  Silicon Creations, a leading supplier of high-performance analog and mixed-signal intellectual property (IP), announced a variety of new IP offerings on TSMC’s N5, N5P, N7, N7+, 12FFC, and 22ULP and 22ULL processes, designed to support customers’ SoC timing and clock demands.
  
  
• Moortec Drives Optimised Performance & Increased Device Reliability on TSMC's N5 and N5P Process Technologies with its Complete In-Chip Monitoring Subsystem (Monday Sep. 23, 2019)
  Moortec, a leading provider of in-chip monitoring and optimisation IP, today announced the availability of its latest In-Chip Monitoring IP Subsystem on TSMC’s N5 and N5P process technologies.
  
  
• Rambus Announces Portfolio of Advanced Memory and SerDes PHYs on TSMC N7 Process (Monday Sep. 23, 2019)
  Rambus, a premier silicon IP and chip provider making data faster and safer, today announced a broad portfolio of high-speed memory and SerDes PHYs for next-generation applications on TSMC’s industry-leading N7 process technology.