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IP / SOC Products News

• Rambus and Synopsys Collaborate to Deliver Provisioning Services for Hardware Secure Modules (Monday Jun. 05, 2017)
  Rambus and Synopsys today announced a new collaboration to accelerate the adoption of advanced security platforms and technologies to protect valuable assets during key and device provisioning.
  
  
• Synopsys and Mellanox Demonstrate Complete PCI Express 4.0 Host and Device System Interoperability (Monday Jun. 05, 2017)
  Synopsys, Inc. today announced it has collaborated with Mellanox Technologies to successfully demonstrate full system interoperability between their two independently developed PCI Express® 4.0 solutions.
  
  
• EnSilica develops sureCore's new, Ultra-Low Power IoT reference platform (Monday Jun. 05, 2017)
  EnSilica, a leading independent provider of semiconductor solutions and IP, and sureCore, the low power SRAM IP leader, have announced that EnSilica has developed sureCore’s new, ultra-low power IoT reference platform targeted principally at the development of the next generation of wearable consumer and medical applications.
  
  
• Chips&Media announced Image Signal Processing (ISP) IP family targeting surveillance and automotive products (Thursday Jun. 01, 2017)
  Chips&Media, Inc., announced the introduction of new Image Signal Processing(ISP) IPs targeting Surveillance and Automotive products. New IP families are developed to specifically support 2MP, 5MP and 8MP sensors and specialized to meet demands of surveillance and automotive products, such as low light environment optimization.
  
  
• CAST Adds DO-254 Avionics Interface Cores though New Partnership with Nolam (Thursday Jun. 01, 2017)
  Semiconductor IP provider CAST, Inc. today announced a new partnership with Nolam Embedded Systems, and the resulting availability through CAST of several Nolam avionics-related IP cores.
  
  
• PLDA at the Epicenter of PCIe 4.0 Wave of Adoption with Recent PCIe Design Conference Achievements and Testing Success for PLDA's Gen4SWITCH (Thursday Jun. 01, 2017)
  PLDA, the industry leader in PCI Express® interface IP solutions, today highlighted recent PCIe® 4.0 milestones, including information and feedback gleaned from its PLDA Design Days event in Shanghaï, as well as its achievements from April’s PCIe-SIG Compliance Workshop testing.
  
  
• Flex Logix Delivers High-Performance, High-Density Embedded FPGA for Deep Learning, Data Center and Base Station Chips (Wednesday May. 31, 2017)
  Flex Logix™ Technologies, Inc., a leading developer of embedded FPGA IP cores and software, today announced it has completed design of its second-generation high-performance IP core for TSMC 16FF+ and 16FFC processes. Enabling embedded FPGA arrays greater than 100,000 LUTs, the new Flex Logix core enables chips to be easily customizable and upgradeable in-field.
  
  
• Synopsys Integrates VESA Display Stream Compression into DesignWare MIPI DSI IP to Enable 4K Ultra HD and Higher Resolution Displays (Wednesday May. 31, 2017)
  Synopsys, Inc. (Nasdaq:SNPS) today announced its integrated DesignWare® MIPI DSI Host Controller IP with the Video Electronics Standards Association (VESA®) Display Stream Compression (DSC) encoder, delivering a complete display IP solution for mobile, augmented/virtual reality and automotive SoCs.
  
  
• Atomic Rules announces DPDK-aware FPGA/GPP data mover (Tuesday May. 30, 2017)
  Atomic Rules, a reconfigurable computing IP firm, is pleased to announce the launch of Arkville, a DPDK-aware FPGA/GPP data mover enabling Linux DPDK applications to offload server cycles to FPGA gates.
  
  
• Programmable Battery Charger IPs For SoC Applications (Monday May. 29, 2017)
  Chipus is building out its power management offerings by expanding its line of battery charger IPs, designed for modern mobile and IoT applications, where battery powered solutions are ubiquitous.
  
  
• Synopsys Announces Availability of DesignWare IP on Samsung 14LPP and 10LPP Process Technologies (Wednesday May. 24, 2017)
  Synopsys, Inc. (Nasdaq:SNPS), today announced availability of a broad portfolio of DesignWare® IP on Samsung Electronics' 14LPP and 10LPP process technologies including USB 3.1/3.0/2.0, PCI Express® 4.0, HDMI 2.1/2.0, LPDDR4 and DDR4.
  
  
• SST Announces Qualification of Smartbit OTP NVM Technology for ON Semiconductor's 110 nm CMOS Process (Wednesday May. 24, 2017)
  Microchip Technology through its Silicon Storage Technology (SST) subsidiary announced that ON Semiconductor, driving energy efficient innovations, has qualified SST’s Smartbit™ One-Time Programmable (OTP) Non-Volatile Memory (NVM) technology for SP110, ON Semiconductor’s 110 nm process node.
  
  
• New SHA-3 hashing IP from Barco Silex helps customers implement future-proof security (Wednesday May. 24, 2017)
  Barco Silex has added the new SHA-3 hashing functions to its extensive offering of IP blocks. Hashing functions are used to check the integrity of messages, transactions and data in, e.g., e-commerce, financial applications or data archiving. SHA-3 hashing is part of the NIST-endorsed FIPS 202 standard and serves as a future-proof backup for the widely-used SHA-2 algorithms.
  
  
• Sidense SHF Memory Macros Target IoT and Other Very Low Power Applications in TSMC's 40ULP Process (Tuesday May. 23, 2017)
  Sidense Corp., a leading developer of non-volatile memory (NVM) IP cores, today announced that the Company’s 1T-NVM macros for TSMC’s 40ULP process have met all TSMC9000 IP Quality Management Program requirements.
  
  
• Synopsys' New Superscalar ARC HS Processors Boost RISC and DSP Performance for High-End Embedded Applications (Tuesday May. 23, 2017)
  Synopsys, Inc. (Nasdaq: SNPS) today announced availability of the new DesignWare® ARC®HS4x and HS4xD processor family for high-performance embedded applications. The ARC HS44, HS46, HS48, HS45D and HS47D processors, available in single-, dual- and quad-core configurations, implement a dual-issue superscalar architecture that delivers up to 6000 DMIPS per core, making it the highest performance processor in the popular ARC HS family.
  
  
• RFEL's Wideband Channeliser - ChannelCore Flex Now Available on the Ettus USRP X310 Platform (Tuesday May. 23, 2017)
  RFEL will be showcasing the latest significant release of its advanced FPGA-based channeliser IP – ChannelCore Flex™ – on stand 27 at EW Europe in London Olympia from 6th to 8th June 2017. The latest enhancement of this award winning IP now offers support for up to 16 wideband inputs, each capable of processing several GHz of bandwidth.
  
  
• IPrium releases 40G LDPC I.6 Encoder/Decoder for DWDM systems (Tuesday May. 23, 2017)
  FPGA intellectual property (IP) provider IPrium LLC (www.iprium.com) today announced that it has expanded its family of Super-FEC IP products with a new OTU3 40G I.6 LDPC Codec IP Core for the G.975.1 standard.
  
  
• Synopsys Delivers Industry's First Multi-Protocol 25G PHY IP in 7-nm FinFET Process (Monday May. 22, 2017)
  Synopsys today announced its new DesignWare® Multi-Protocol 25G PHY IP for high-performance computing applicationslligence. The PHY IP gives designers the flexibility to efficiently integrate multiple protocols including PCI Express® 4.0, 25G Ethernet, SATA and CCIX into system-on-chips (SoCs) targeting the 7-nanometer (nm) and 16-nm FinFET processes
  
  
• Dolphin Integration unveils its new generation of 32-kHz oscillators for IoT and wearable applications (Monday May. 22, 2017)
  Dolphin Integration announces today the addition of ultra-low power 32.768- kHz oscillators dedicated to always-on power domains, at 55 nm and at 22 nm.
  
  
• Rambus, PLDA and Avery Design Announce Comprehensive PCIe 4.0 Solution (Thursday May. 18, 2017)
  Rambus today announced it is collaborating with PLDA, the industry leader in PCI Express® controller IP solutions, and Avery Design Systems Inc., an innovator in functional verification productivity solutions, to offer a comprehensive, silicon-proven PCI Express (PCIe) 4.0 solution, with backward compatibility to PCIe 3.0 and 2.0.
  
  
• Alma Technologies Introduces an Online Tool for Comparison of Image Compression Standards (Wednesday May. 17, 2017)
  An online tool for back-to-back comparison of the image compression standards implemented by our IP cores is now available on our website. The Bit Accurate Models of the respective image compression cores are used to encode / decode a user supplied test image, in order to evaluate and compare their actual performance.
  
  
• Faraday Introduces UrLib+ Add-on Library on UMC 40LP Process (Tuesday May. 16, 2017)
  Faraday today introduced its new UrLib+™ add-on library for the third-party library on UMC 40LP process technology. UrLib+ is a library package, featuring extra sets of cells for optimized PPA (Power/Performance/Area), yield controllability, clock tree noise reduction, robust ESD protection, and lower ECO cost over the traditional physical libraries.
  
  
• eMemory Taps into IoT Markets with its Game-Changing Security IP (Monday May. 15, 2017)
  As Physical Unclonable Functions (PUFs) have become an increasingly popular security technology, eMemory (TPE:3529) today announced the launch of NeoPUF, a game-changing IP innovation which equips every single chip with its own unique “fingerprint”, to capitalize on the growing security demand among IoT applications.
  
  
• Imagination announces first PowerVR Series8XT IP core based on new Furian GPU architecture (Wednesday May. 10, 2017)
  Imagination Technologies (IMG.L) announces the first GPU IP core based on its new PowerVR Furian architecture, the Series8XT GT8525. Furian is designed to enable a new generation of consumer devices to deliver high-resolution, immersive graphics content and data computation for sustained time periods within mobile power budgets.
  
  
• Andes, First Mainstream CPU IP Provider to Adopt RISC-V, Expands Product Line with New 64bit Processor IP (Wednesday May. 10, 2017)
  Andes Technology today announced a new generation of the AndeStar™ architecture. In the process, Andes becomes the first mainstream CPU IP provider to adopt RISC-V, the open RISC Instruction Set Architecture (ISA) developed at the University of California Berkeley.
  
  
• Sonics And Northwest Logic Partner On High Throughput Memory Subsytem Solutions (Tuesday May. 09, 2017)
  Sonics and Northwest Logic today announced their partnership to deliver high throughput memory subsystem solutions for complex System-On-Chip (SOC) designs.
  
  
• Credo Unveils Robust Portfolio of 56G and 112G PAM-4 PHY Connectivity Solutions (Monday May. 08, 2017)
  Credo Semiconductor today announced a comprehensive portfolio of 56G and 112G PAM-4 PHY devices, enabling connectivity for enterprise, hyperscale datacenter, and service provider networks.
  
  
• SiFive Launches CPU IP Industry into the Cloud with New RISC-V Cores and an Easy Online Business Model (Thursday May. 04, 2017)
  SiFive, the company founded by the inventors of the free and open RISC-V instruction set architecture (ISA), today announced the immediate availability of its Coreplex IP, the fastest and easiest way to license RISC-V cores.
  
  
• Hitek Announces Ultra Low Latency 10G Ethernet FPGA IP Core Integrated with Solarflare SFA7942Q AOE (Thursday May. 04, 2017)
  Hitek Systems, a leading FPGA IP core development and FPGA / hardware design services firm, announced the availability of the industry leading Ultra Low Latency 10Gbps Ethernet FPGA IP Core solution integrated with the Solarflare® SFA7942Q ApplicationOnload™ Engine (AOE).
  
  
• VeriSilicon's Vivante VIP8000 Neural Network Processor IP Delivers Over 3 Tera MACs Per Second (Wednesday May. 03, 2017)
  VeriSilicon Holdings Co., Ltd. (VeriSilicon), a Silicon Platform as a Service (SiPaaS®) company, today announces VIP8000, a highly scalable and programmable processor for computer vision and artificial intelligence.