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IP / SOC Products News

• IP Controller Core CAN 2.0b and CAN FD of Fraunhofer IPMS certified according to ISO security standard (Thursday Oct. 03, 2019)
  Fraunhofer IPMS has certified its IP designs, CAN 2.0B and CAN FD Controller Core, for functional safety according to ISO26262:2018. System integrators can now be sure that this IP Core fulfills all criteria of the ASIL B level requirements.
  
  
• Adesto and Cadence Collaborate to Expand xSPI Ecosystem for Emerging IoT Devices (Wednesday Oct. 02, 2019)
  The Cadence® Memory Model for xSPI is the first commercially available model that allows customers to ensure optimal use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto®’s EcoXiP™ octal xSPI non-volatile memory (NVM).
  
  
• Data Compression Accelerators from CAST Now Available on Xilinx Alveo Boards (Friday Sep. 27, 2019)
  Semiconductor intellectual property (IP) provider CAST, Inc. today announced that its GZIP/ZLIB/Deflate Compression and Decompression reference designs are now available on Xilinx® Alveo™ Data Center Accelerator Cards.
  
  
• Sofics releases pre-silicon analog I/O's for high-speed SerDes for TSMC N5 process technology (Friday Sep. 27, 2019)
  Sofics bvba, a leading semiconductor integrated circuit IP provider announced that it has expanded its TakeCharge® Electrostatic Discharge (ESD) and Analog I/O portfolio with solutions for TSMC’s N5 process technology. The cells enable high speed and high frequency interfaces.
  
  
• SiFive Announces Key Enablement Of Trace And Debug (Thursday Sep. 26, 2019)
  SiFive, Inc., has announced the general availability of the latest update to SiFive Core IP and SiFive Core Designer in the Q3 2019 quarterly update. This release is specifically focused on the enablement of Trace and Debug functionality in the development of configurable SoC design.
  
  
• Synopsys and TSMC Collaborate to Develop Portfolio of DesignWare IP for TSMC 5nm FinFET Plus (N5P) Process (Thursday Sep. 26, 2019)
  Synopsys today announced a collaboration with TSMC to develop a broad portfolio of DesignWare® interface IP, logic libraries, embedded memories, and one-time programmable (OTP) non-volatile memory (NVM) IP on TSMC's 5-nanometer (nm) FinFET Plus (N5P) Process.
  
  
• Rambus Tapes Out 112G XSR SerDes PHY on Leading-edge 7nm Process (Thursday Sep. 26, 2019)
  Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced the tapeout of its 112G XSR SerDes PHY on a leading-edge 7nm process node optimized for PPA to support data center, networking, HPC, AI and ML applications.
  
  
• Analog Bits Showcases Silicon of Analog and Mixed Signal IP Products on TSMC N7 Process Targeting Automotive Grade with Split Corner Lots and PVT Characterization Results Available (Thursday Sep. 26, 2019)
  Analog Bits, an industry leading provider of low-power mixed-signal IP (Intellectual Property) solutions is demonstrating its silicon results targeting automotive grade for its analog and mixed signal IP products on TSMC's N7 process
  
  
• Synopsys Extends Portfolio of Cloud Computing IP with 112G Ethernet PHY for Hyperscale Data Center SoCs (Wednesday Sep. 25, 2019)
  Synopsys Extends Portfolio of Cloud Computing IP with 112G Ethernet PHY for Hyperscale Data Center SoCs
  
  
• Evaluation Boards Now Available for Flex Logix EFLX4K eFPGA on GLOBALFOUNDRIES' Most Advanced FinFET Platform (Wednesday Sep. 25, 2019)
  Flex Logix Technologies, Inc., the leading supplier of embedded FPGA (eFPGA) IP and software, today announced that it has received working first silicon of its validation chip for the EFLX 4K eFPGA IP cores running on GLOBALFOUNDRIES (GF) 12nm Leading-Performance (12LP) FinFET platform and newly announced 12LP+ solution.
  
  
• M31 Technology Develops Optimized IP Solutions on Multiple TSMC Specialty Processes (Wednesday Sep. 25, 2019)
  M31 Technology announced its series of developments geared to optimized IP solutions for TSMC's specialty processes. The development ultimate goal is to assist chip designers in achieving low power consumption, high performance, compact size, and place & route convenience.
  
  
• Analog Bits and Aragio Solutions Team Up with GLOBALFOUNDRIES to Deliver Automotive IP Solutions (Tuesday Sep. 24, 2019)
  GLOBALFOUNDRIES (GF), Analog Bits and Aragio Solutions (Aragio) announced today at GF’s annual Global Technology Conference (GTC) that they are collaborating to develop a portfolio of I/O libraries on GF’s 22nm FD-SOI (22FDX®) platform.
  
  
• Silicon Creations to Showcase PLL Developments on 22nm to 5nm Processes at TSMC 2019 Open Innovation Platform Ecosystem Forum (Monday Sep. 23, 2019)
  Silicon Creations, a leading supplier of high-performance analog and mixed-signal intellectual property (IP), announced a variety of new IP offerings on TSMC’s N5, N5P, N7, N7+, 12FFC, and 22ULP and 22ULL processes, designed to support customers’ SoC timing and clock demands.
  
  
• Moortec Drives Optimised Performance & Increased Device Reliability on TSMC's N5 and N5P Process Technologies with its Complete In-Chip Monitoring Subsystem (Monday Sep. 23, 2019)
  Moortec, a leading provider of in-chip monitoring and optimisation IP, today announced the availability of its latest In-Chip Monitoring IP Subsystem on TSMC’s N5 and N5P process technologies.
  
  
• Rambus Announces Portfolio of Advanced Memory and SerDes PHYs on TSMC N7 Process (Monday Sep. 23, 2019)
  Rambus, a premier silicon IP and chip provider making data faster and safer, today announced a broad portfolio of high-speed memory and SerDes PHYs for next-generation applications on TSMC’s industry-leading N7 process technology.
  
  
• Spectral Design and Test Inc., Announces a New Family of MemoryIP Targeted at the 5G Market (Monday Sep. 23, 2019)
  Spectral Design & Test Inc. (SDT), a leading provider of embedded Memory Development platform is announcing a portfolio of Memory Compilers targeted at 5G applications that include base stations & edge IOT markets.
  
  
• eSilicon Announces Availability of 7nm High-Bandwidth Interconnect (HBI+) PHY for Die-to-Die Interconnects (Monday Sep. 23, 2019)
  eSilicon announced today its 7nm high-bandwidth interconnect (HBI™)+ physical interface (PHY) IP is available to be licensed for inclusion in customer designs.
  
  
• CAST CAN 2.0/FD Bus IP is Safety-Ready with ISO 26262 Certification (Friday Sep. 20, 2019)
  CAST, Inc. today announced that its CAN 2.0 and CAN FD Bus Controller IP Core is certified as ISO 26262 ASIL-B ready. The company believes this is the first such CAN IP core to receive ISO 26262 certification.
  
  
• SmartDV Announces Availability of Ethernet TSN Design IP (Tuesday Sep. 17, 2019)
  SmartDV™ Technologies today announced its Design IP for the Ethernet Time-Sensitive Networking (TSN) protocol, an update to the IEEE standard for time-sensitive transmission of data over Ethernet networks.
  
  
• CEVA Introduces New AI Inference Processor Architecture for Edge Devices with Co-processing Support for Custom Neural Network Engines (Tuesday Sep. 17, 2019)
  CEVA today announced from AutoSens in Brussels, Belgium, NeuPro-S, its second-generation AI processor architecture for deep neural network inferencing at the edge.
  
  
• Synopsys' New Embedded Vision Processor IP Delivers Industry-Leading 35 TOPS Performance for Artificial Intelligence SoCs (Monday Sep. 16, 2019)
  DesignWare ARC EV7x Vision Processors with Deep Neural Network Accelerator Provide More Than 4X Performance Increase for AI-intensive Edge Applications
  
  
• Synopsys Simplifies Automotive SoC Development with New ARC Functional Safety Processor IP (Monday Sep. 16, 2019)
  Expanded Portfolio of ISO 26262 ASIL B and ASIL D Compliant DesignWare ARC Processors Accelerate Safety Certification of ADAS, Radar/LiDAR, and Automotive Sensor SoCs
  
  
• Silex Insight releases ARIA crypto engine for the Korean market (Thursday Sep. 12, 2019)
  Silex Insight, the leading provider of embedded Security IP, extends its broad range of Cryptographic IP cores with the release of the ARIA crypto engine, the block cipher standard in Korea.
  
  
• AGIC C-Fuse OTP High-Temperature-Immunity Tailored for AEC-Q100 Grade 0 Applications (Thursday Sep. 12, 2019)
  AGI Corporation (AGIC) announced that AGIC C-Fuse OTP macros are tailored for AEC-Q100 Grade 0 applications that require high reliable operation and long-life data retention in high-temperature environments.
  
  
• Synopsys Delivers Industry's First Compute Express Link (CXL) IP Solution for Breakthrough Performance in Data-Intensive SoCs (Wednesday Sep. 11, 2019)
  Synopsys, Inc. (Nasdaq: SNPS) today announced availability of its complete DesignWare® Compute Express Link (CXL) IP solution consisting of controller, PHY, and verification IP for AI, memory expansion, and high-end cloud computing system-on-chips (SoCs).
  
  
• PLDA Achieves PCI Express 4.0 Compliance for its XpressRICH PCIe Controller IP During the First Official PCI-SIG PCIe 4.0 Compliance Workshop (Monday Sep. 09, 2019)
  PLDA, the industry leader in PCI Express® IP and data interconnect solutions, today announced that their XpressRICH™ PCIe® Controller IP passed all Gold and Interoperability tests at the PCI-SIG® Compliance Workshop, held in August 2019 in Burlingame, CA.
  
  
• eMemory IP Garners Most Stringent Level of Certification for Automotive Applications (Monday Sep. 09, 2019)
  eMemory, the semiconductor industry’s leading provider of non-volatile memory intellectual property, has won key certifications for its technology in automotive applications. eMemory is the only company in the greater China region to receive these dual IP certifications.
  
  
• PUFsecurity Leverages NeoPUF to Lead Hardware Security Technology (Friday Sep. 06, 2019)
  Charles Hsu, the chairman of eMemory, the world’s seventh largest supplier of semiconductor-based intellectual property (IP), believes that his company has found the solution to an expensive and urgent cybersecurity problem. His company is spinning off PUFsecurity to popularize PUF technology in the marketplace.
  
  
• Silex Insight and Wave Computing Collaborate to Deliver Security-Conscious Artificial Intelligence (AI) Platforms Across Enterprise and Automotive Markets (Thursday Sep. 05, 2019)
  
  
  
• Credo Announces Production Availability of HiWire Active Electrical Cables (Wednesday Sep. 04, 2019)
  Credo, a global innovation leader in Serializer-Deserializer (SerDes) technology which delivers high performance, low power connectivity solutions for 100G, 400G, and 800G port enabled networks, today announced the production availability of HiWire™ Active Electrical Cables (AEC).