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1 – 33Gbps C2C SerDes PHY
The AXLinkIO C2C IP utilizes the silicon-proven AXLinkIO transceiver architecture for short-reach type of channel links.
The AXLinkIO C2C IP from AnalogX is compatible to several protocols including JESD, OIF, Ethernet C-C, CPRI, and others.
The AXLinkIO C2C IP from AnalogX is compatible to several protocols including JESD, OIF, Ethernet C-C, CPRI, and others.
Features
- 1 - 33 Gbps continuous operation
- 1.8 mW/Gbps
- World’s best area and latency in segment
- Channel loss support up to 18dB
- Supports both AC and DC
- Standard two supplies and devices
- Supports any lane configuration up to x20 per macro
- No external components nor special packaging requirements
- Integrates seamlessly with extensive test & configuration software and features
- Available in 16/12nm FINFET technology
Benefits
- World Class Support
- Multilingual 24h support
- Full support from IP delivery to production
- Designated IP Applications Engineer
- Direct access to IP IC Design team
- Configuration Software
- User-friendly master configuration software
- Complete IP register access
- Extensive BIST programming features
- Internal Eye Diagram generator
Deliverables
- Physical layout view (GDSII)
- CDL netlist
- Layout exchange format LEF view
- Liberty timing models (.lib)
- Verilog model and testbenches
- ATPG models
- IBIS-AMI models
- Master configuration software
- Datasheet and application notes
- Integration guides
- Silicon characterization report
Applications
- Tailored and optimized for processor, Chip-to-Chip, and Chip-to-Module connectivity.
Block Diagram of the 1 – 33Gbps C2C SerDes PHY IP Core
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