The synthesizer produces stable clock signal in range from 1 to 600MHz. PLL with integer factors of the frequency division is used for synthesis.
External reference clock 6 MHz connects with pll_iclk input. The output of the frequency synthesizer forms a stable signal with a frequency from 1 to 600 MHz The range of possible frequencies is set by the dividing ratio control register pll_cfg<9:0> and output frequency is the register value in Mhz. The synthesizer is OFF if value register is 000h.
The device is designed with TSMC CMOS 90 nm technology.