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UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
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LVDS Deserializer - 1.25 Gbps 4-Channel
The 4-Channel LVDS Deserializer is a high performance 4-channel LVDS Receiver implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 180MHz. The Receiver is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the receiver margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
Features
- 25-180 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5.0 Gbps data throughput
- Full Low power CMOS design
- Power Down mode
- Low swing LVDS devices for low EMI
- PLL requires no external components
- 7/10 bit programmable serial data transmitted per pixel clock per cannel
- Perfect companion for our 4-Channel LVDS Serializer with pre-emphasis, the MXL-SR-LVDS-4CH
- Compatible with TIA/EIA-644 LVDS Standard
Deliverables
- Data Sheet
- GDSII
- LVS Netlist
- Integration Guidelines
- Synopsis timing Model
- Behavioral Model
- LEF File for P&R
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