32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
1.25 Gbps SGMII SerDes
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Block Diagram of the 1.25 Gbps SGMII SerDes IP Core
SerDes IP
- 250Mbps to 12.7Gbps Multiprotocol SerDes PMA
- 125Mbps to 16Gbps Multi-protocol SerDes PMA
- 250Mbps to 8.1Gbps Multi-protocol SerDes PMA, wire-bond
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency