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1.2GHz Programmable PLL
This customizable PLL has been designed for use with high performance A/D converters such as S3’s 10-bit 80MSPS pipeline ADC, where low jitter clock generation is critical to the success of applications such as DVB and Cable Modem.
This PLL is an integer N PLL, giving the best jitter performance, with a flexible large range of programmable input, frequency and output dividers.
The PLL is designed to provide excellent jitter performance while also maintaining low current consumption by using a third order loop filter which gives the best spurious performance, supply rejection, phase noise and jitter performance.
The PLL has been implemented in a standard 90nm basic logic process with no analog options. It is readily portable to any similar manufacturing process, and any activity of this nature is fully supported.
This PLL is an integer N PLL, giving the best jitter performance, with a flexible large range of programmable input, frequency and output dividers.
The PLL is designed to provide excellent jitter performance while also maintaining low current consumption by using a third order loop filter which gives the best spurious performance, supply rejection, phase noise and jitter performance.
The PLL has been implemented in a standard 90nm basic logic process with no analog options. It is readily portable to any similar manufacturing process, and any activity of this nature is fully supported.
Features
- 90nm 6 metal CMOS (No analog options)
- 1.2V power supply
- Four Programmable Output Dividers
- Phase detector frequency: 5MHz to 20MHz
- Max input frequency (clkin): 200MHz
- Feedback divider range (N): 1 to 512
- Output divider range (M): 1 to 63
- Reference Divider (R): 1 to 63
- Period Jitter: 5ps
- Cycle-to-Cycle Jitter: 8.5ps rms
- Long Term Jitter over 20us:
- 14ps rms for Fin = 20MHz, Fout = 640MHz
- Very Low Phase Noise,
- Integrated @ 20MHz = -66.9dBc
- 50dBc largest spur of reference clock
- Die area of 0.2mm2 (including bandgap reference)
- Power Dissipation < 4mW
- No external components
Benefits
- Designed for the most demanding applications that require very low jitter clocks such as clocking high performance data converters in applications such as DVB and Cable Modem.
- The PLL supports a wide range of reference lock frequencies programmed via digital bits including selection of optimum loop filter bandwidth.
- The area and current consumption are small.
- The PLL has been developed on standard 90nm process with no analog options. The PLL can be ported to any similar process.
- An optional lock detect signal is available.
- A programmable feedback divider provides a VCO frequency resolution equal to the PFD frequency.
- A programmable output divider can be selected as well as the VCO output.
Deliverables
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (tlf)
- Behavioral Model (VHDL/Verilog)
- Silicon Samples
- DemonstrationEvaluation Board
- Integration Support
Block Diagram of the 1.2GHz Programmable PLL IP Core
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