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1.4MHz Bandwidth CTSD ADC

The S3ADSD3M14BT40ULP is a highly-compact and ultralow power Continuous-Time Sigma-Delta ADC with an input Signal Bandwidth of 1.4MHz.

This IP includes a first-order Anti-Aliasing filtering function. Noise Shaping is implemented with a 3rd Order Modulator.

For application flexibility, this IP includes a Reference Buffer.

Working at 200MHz clock frequency, this ADC features an outstanding performance that includes 75.0dB Dynamic Range, 68.5dB SNR and 11.0-bit ENOB.

Excluding the Digital Decimation filter, this ADC power
dissipation is only 450uW and occupies only 0.03mm2 area.

Features

TSMC 40nm ULP Process
No Analog Options
1.1V & 1.8V Supplies
Continuous-Time Sigma-Delta ADC
Built-In 1st Order Anti-Aliasing Filter
External Reference w/ Internal Buffer
1.4MHz Input Signal Bandwidth
200MHz Output Bitstream
200MHz Input Clock Frequency
Input Signal Range: 1.0Vppdiff
Outstanding Performance:

75.0dB Dynamic Range
68.5dB SNR
68.0dB SNDR
11.0-bit ENOB

Ultra Low Power Dissipation: 450uW
Highly Compact Die Area: 0.03mm2
(Decimation Filter not included)

Benefits

The S3ADSD3M14BT40ULP does not require any special analog process options.

Deliverables

Datasheet
Characterization Report
Flat Netlist (cdl)
Layout View (gds2)
Abstract View (lef)
Timing View (lib)
Behavioural Model (Verilog .v)
Integration Guidelines and Support
*Subject to Agreement

Applications

Wireless Communications: LTE-M
Wireline Communication Networks

Block Diagram of the 1.4MHz Bandwidth CTSD ADC IP Core

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