1.6 Gbit/s CCSDS (8160,7136) LDPC Decoder
In each clock cycle, 12 check nodes (12x32 = 384 messages) or 96 variable nodes (96x4 = 384 messages) are fully decoded. Each iteration requires 86 clock cycles to calculate the check or variable messages plus a 7 clock cycle pipeline delay. The scaled min–sum iterative decoding algorithm  is used.
The LDPC decoder can achieve up to 1650 Mbit/s with 10 iterations using a 216 MHz internal clock. Optional early stopping allows the decoder to reduce power consumption with little degradation in performance.
The decoder contains two sets of message memories so that check and variable calculations can be performed in parallel. Two input memories are used to buffer the input data.
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