The LDPC Decoder is a fully compatible CCSDS rate 223/255 (8160,7136) LDPC  error control decoder. A regular quasic–cyclic LDPC code with 511x511 square circulants with weight 2 in the parity check matrix is used. There are 2x16 circulants, resulting in a check node degree of 32 and a variable node degree of 4.
In each clock cycle, 12 check nodes (12x32 = 384 messages) or 96 variable nodes (96x4 = 384 messages) are fully decoded. Each iteration requires 86 clock cycles to calculate the check or variable messages plus a 7 clock cycle pipeline delay. The scaled min–sum iterative decoding algorithm  is used.
The LDPC decoder can achieve up to 1650 Mbit/s with 10 iterations using a 216 MHz internal clock. Optional early stopping allows the decoder to reduce power consumption with little degradation in performance.
The decoder contains two sets of message memories so that check and variable calculations can be performed in parallel. Two input memories are used to buffer the input data.
- CCSDS compatible
- Rate 223/255 (8160,7136)
- Includes ping-pong input and output memories
- Up to 225 MHz internal clock
- Up to 1.6 Gbit/s with 10 decoder iterations
- 6-bit sign-magnitude input data
- Up to 64 iterations
- Scaled min-sum decoding algorithm
- Optional power efficient early stopping
- Parity check output
- Xilinx LUTs: 30.4K Virtex-4, 29.1K Virtex-5, 29.4K Virtex-6 and 7-Series, 166 18KB BlockRAMs. Altera ALUTs 26.9K, 166 M9Ks
- Available as EDIF core and VHDL simulation core for Xilinx Virtex-II, Spartan-3, Virtex-4, Virtex-5, Virtex-6, Spartan-6 and 7-Series FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores available on request.
- Available as VHDL core for ASICs
- Low cost university license also available
- All licenses
- EDIF core
- VHDL simulation core
- Test vector generation software
- VHDL ASIC License
Block Diagram of the 1.6 Gbit/s CCSDS (8160,7136) LDPC Decoder IP Core