The LDPC Encoder is a fully compatible CCSDS rate 223/255 (8160,7136) LDPC error control encoder.
A regular quasic–cyclic LDPC code with 511x511 square circulants with weight 2 in the parity check matrix is used. There are 2x16 circulants, resulting in a check node degree of 32 and a variable node degree of 4.
- CCSDS compatible
- Rate 223/255 (8160,7136)
- Up to 250 MHz internal clock
- Up to 1.75 Gbit/s input data rate
- 8-bit byte input and output
- Xilinx LUTs: 12.3K Spartan 3 and Virtex-4, 9.2K Virtex 5, Virtex 6, Spartan 6 and 7-Series. Altera ALUTs 10.2K.
- Available as EDIF core and VHDL simulation core for Xilinx Virtex-II, Spartan-3, Virtex-4, Virtex-5, Virtex-6, Spartan-6 and 7-Series FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores available on request.
- Available as VHDL core for ASICs
- Low cost university license also available
- All licenses
- EDIF core
- VHDL simulation core
- Test vector generation software
- VHDL ASIC License
Block Diagram of the 1.75 Gbit/s CCSDS (8160,7136) LDPC Encoder IP Core