LVDS18 TX CUP and LVDS18 VREF CUP belong to SGIO IO T040GP, which is Sankalp’s General Purpose IO library in 40nm TSMC G process. LVDS18 TX CUP is a LVDS cell which operates on 1.8 V supply, at frequencies upto 675 MHz (1350 Mbps). Power supply sequencing independent (PSSI), Wire bond & Flip chip compatiblity are the salient features for this cell. Cell dimensions are 50µm x 200µm.
- Compatible to IEEE 1596.3-1996 specification
- R programmability option provided to meet output impedance specification
- Implemented in 40nm single poly (TSMC G+ process). It uses 1.0V Oxide and 1.8V Oxide devices. No deep NW, ESD implant or LVT devices required. The reliability voltages of the 1.8V MOS are Vdb = 3.63V and Vxx = 1.98V.
- Operates at frequencies up to 675 MHz or 1350 Mbps
- Weak pull-downs of 20kW are provided on the differential outputs. This is to prevent leakage currents from making the output voltage float significantly above ground. The pull downs are controlled independently with an active high pull down control.
- The core Supply (VDD) is 0.9V ±10% or 1.0V ± 10%.
- I/O Supply (VDDO) is 1.8V ±10
- Operates over temperature range of −40C to 125C
- ESD hardness of 2 kV HBM and 500 V CDM
- Latchup immune upto ±100 mA current injection
- The reference voltage VREF of 1.2V is intended to be supplied through a separate pad called LVDS18 VREF. (Necessity of VREF is being evaluated)
- Wire-bond and Flip-chip compatible
- Programmable weak pull-down
- Supports 8-layer (602) or 9-layer (702) metallization with Circuit-Under-Pad (CUP)
- One I/O supply power/ground pair per 2 TX
- Power supply sequence independent (PSSI)
- LVDS18 TX library has the following cells: LVDS18 TX (50μm by 200µm) LVDS18 VREF (25μm by 170µm). (This development is dependent on necessity of VREF)
- Services Available with this Product
- SOC Integration
- Application & ESD Guidance
- Signal Integrity Analysis & Guidelines
- Characterization Support
- LVS netlist
- Verilog Model
- Timing Model