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1.8V Fault Tolerant General Purpose I/O Inline Pad Set
The 1.8V GPIO FT library provides ultra low leakage general purpose bidirectional I/O cells. These programmable, multi-voltage I/O’s give the system designer the flexibility to design to a wide range of performance targets.
These 22nm libraries are available in inline and staggered CUP wire bond implementations with a flip chip option.
To design a functional I/O power domain with these cells, an additional library is required – 1.8V Support: Power. That library contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
These 22nm libraries are available in inline and staggered CUP wire bond implementations with a flip chip option.
To design a functional I/O power domain with these cells, an additional library is required – 1.8V Support: Power. That library contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
Features
- Bidirectional GPIO Driver Features
- Ultra low leakage
- Multi-Voltage (1.2V, 1.5V, 1.8V)
- LVCMOS / LVTTL input with selectable hysteresis
- Programmable drive strength (rated 2mA to 12mA)
- Selectable output slew rate
- Optimized for EMC with SSO factor of 8
- Open-drain output mode
- Programmable input options (pull-up/pull-down/repeater)
- Power sequencing independent design with Power-On Control
Deliverables
- Physical abstract in LEF format (.lef)
- Timing models in Synopsys Liberty formats (.lib and .db)
- Calibre compatible LVS netlist in CDL format (.cdl)
- GDSII stream (.gds)
- Behavioral Verilog (.v)
- Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- Databook (.pdf)
- Library User Guide - ESD Guidelines (.pdf)
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IO
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- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- LDO Capless Fast Response Series ( Vin = 1.65-1-95V; Vo = 0-75-1.0V; Io = 150 mA ) - TSMC 28nm
- Low capacitance analog IO
- Low Leakage Analog IO Pads