LVDS18 TX and LVDS18 VREF belong to Sankalp’s 28nm IO library. Power supply sequencing independent (PSSI), 9-layer metallization and Circuit-under-Pad are the salient features for this cell. The foot print of LVDS18 TX is 70μm x 185μm and that of LVDS18 VREF is 35μm x 185μm. Available in both North-South and East-West layout variants
- Supports 9-layer (702) metallization with Circuit-Under-Pad (CUP).
- Weak pull-downs of 20KOhms are provided on the differential outputs.
- Operates over junction temperature ranges from -40 to 125 degrees Celsius.
- The core Supply (VDD) is 0.9V ± 10% or 1.0V +5%,-10%.
- I/O Supply (VDDO) is 1.8V ± 10%.
- Operates for frequencies up to 1GHz or 2Gbps data rate
- No Power supply sequence restrictions.
- ESD hardness of 2KV HBM, 500V CDM and +/-100mA current injection for latch up.
- Sankalp’s process optimized General Purpose cell set is very comprehensive and it would meet the critical performance, power, area, and reliability requirements for today’s system-on-chip design
- Low power
- Smaller Foot Print
- Higher Pad to PG ratio
- Faster Integration
- Services Available with this Product
- SOC Integration
- Application & ESD Guidance
- Signal Integrity Analysis & Guidelines
- Characterization Support
- LVS netlist
- Verilog Model
- Timing Model