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1 to 400 Gigabit Universal Ethernet MAC IP Core
The 1 to 400 Gigabit Universal Ethernet MAC IP core is IEEE compliant.
The Universal MAC supports all Ethernet Flavors from 1GE to 400GE with a single code base. The core targets FPGA and ASIC operation. The user transmit & receive interface is through a user programmable FIFO. The FIFO can run synchronous or asynchronous, and the FIFO width is programmable by the user. The line interface is through xMII. The core is plug and play with any PCS running xMII, or it can be delivered with a Tamba PCS core.
The Universal MAC supports all Ethernet Flavors from 1GE to 400GE with a single code base. The core targets FPGA and ASIC operation. The user transmit & receive interface is through a user programmable FIFO. The FIFO can run synchronous or asynchronous, and the FIFO width is programmable by the user. The line interface is through xMII. The core is plug and play with any PCS running xMII, or it can be delivered with a Tamba PCS core.
Features
- 1 to 400Gbps in FPGA, 1 to 1,000 Gbps in ASIC
- Single RTL code base supports all speed variations.
- Supports Altera, Xilinx, Microsemi FPGA and ASIC.
- Full MAC layer and Reconciliation sub-layer implementation compliant with IEEE802.3
- Configurable IPG with DIC from 1 byte to 48 bytes. Note, 12 bytes is the standard, and the default mode.
- Configurable Preamble size and contents
- Configurable Transmit Pad insertion.
- Port and Class of Service Pause Frame support
- CRC-32 insertion and checking at line-rate
- 100% bandwidth through implementation of Deficit Idle Counter (DIC)
- Full handling on transmit & receive FIFO overflow & underrun.
- Jumbo frame support
- Transmit and Receive Statistics Vector
- Local Loopback
- PHY error and fault signaling provided by Reconciliation sub-layer
- Frequency independence; the Tx and Rx MAC can be gapped down to any logical bandwidth
- PCS Cores: 10GbaseR, XAUI, RXAUI, DXAUI, 40G/100G PCS/MLD, 400G PCS/MLD Pre-standard
- FEC Cores: 10G-KR
Benefits
- Lowest latency core on the market, e.g;
- 10GE “FIFO+MAC+PCS” <7ns in ASIC
- 10GE “FIFO+MAC+PCS” <25ns in Altera Stratix V-3
- Lowest gate count core on the market.
- Large timing margin: cores will often run in the slowest speed grade saving money, and compile with push button ease in minutes.
- Single code base for all versions, which drastically reduces internal support and learning curve.
- Customizable synthesis for any speed/target technology. FPGA or ASIC, 65nM or 14nM ASIC node the RTL can be configured to add or drop pipeline stages to yield the best performing core for the target technology.
Deliverables
- Deliver one code base, as machine readable source (RTL)
- Test bench, synthesis scripts.
- Can generate any version required and use internally for any what if scenarios. Only pay for the version that will be used in the project.
- Datasheet, Userguide, Product Brief, SDC files
Block Diagram of the 1 to 400 Gigabit Universal Ethernet MAC IP Core
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