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1 to 400 Gigabit Universal Ethernet MAC IP Core
The 1 to 400 Gigabit Universal Ethernet MAC IP core is IEEE compliant.
The Universal MAC supports all Ethernet Flavors from 1GE to 400GE with a single code base. The core targets FPGA and ASIC operation. The user transmit & receive interface is through a user programmable FIFO. The FIFO can run synchronous or asynchronous, and the FIFO width is programmable by the user. The line interface is through xMII. The core is plug and play with any PCS running xMII, or it can be delivered with a Tamba PCS core.
The Universal MAC supports all Ethernet Flavors from 1GE to 400GE with a single code base. The core targets FPGA and ASIC operation. The user transmit & receive interface is through a user programmable FIFO. The FIFO can run synchronous or asynchronous, and the FIFO width is programmable by the user. The line interface is through xMII. The core is plug and play with any PCS running xMII, or it can be delivered with a Tamba PCS core.
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Block Diagram of the 1 to 400 Gigabit Universal Ethernet MAC IP Core
Ethernet MAC IP
- 10 Gigabit Ethernet XGMAC IP
- 10-Gbps Ultra-Low Latency Ethernet MAC & PCS (10GBASE-R)
- 40-Gbps Ultra-Low Latency Ethernet MAC & PCS (40GBASE-R4)
- 100-Gbps Ultra-Low Latency Ethernet MAC & PCS (100GBASE-R4, 100GBASE-R10)
- 25-Gbps Ultra-Low Latency Ethernet MAC & PCS + RS-FEC
- 10/100/1000 MBit Ethernet MAC