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100 dB of SNR, 24-bit multichannel audio CODEC with embedded regulator and high CMRR
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10/100/1000 Base-T Ethernet PHY IP (Silicon Proven in ST28FDSOI)
The GPHY is a highly integrated single chip for Giga 10/100/1000 Ethernet application with low power consumption. It supports 10BASE-T, 100BASE-TX,1000BASE-T operation. This GPHY connects the Media Access Control Layer (MAC) by GMII(Giga Media Independent Interface).
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Block Diagram of the 10/100/1000 Base-T Ethernet PHY IP (Silicon Proven in ST28FDSOI)
