The 1000Base-X PCS Core is compliant with Clause 36 of the IEEE802.3 standard and implements 8B/10B coding, link synchronization, frame encapsulation generation / termination. The Core also supports Auto-Negotiation (Clause 37 of IEEE802.3 standard), which is used to automatically, or under user application software control, exchange ability information between the Core and the remote end of the link and configure the Core to take the best advantage on the advertised features of the Remote node.
The PCS Core can be used with SGMII PHYs, supports SGMII 10/100 or Gigabit operation with data duplication and SGMII Auto-Negotiation according to the Cisco specification. The core can seamlessly connect to any industry standard Gigabit Ethernet SERDES (SERializer / DESerializer) device via a Gigabit TBI (Ten Bit Interface) and to MAC Layer device with a standard GMII (Gigabit Medium Independent Interface) for Gigabit operation or MII (Medium Independent Interface) for 10/100Mbps operation.
The core is optionally delivered in generic synthesizable HDL (VHDL or Verilog) code (For use in Altera FPGA or ASIC technologies), or as a FPGA netlist, which provides a lower cost IP solution.
- 1000Base-X PCS with SGMII rate converters to support 10/100/1000 Mbps speeds.
- Autonegotiation with automatic speed selection
- Low Latency Core without FIFOs and clock multiplexers
- 802.3az Energy Efficient Ethernet (EEE) support
- Interface Options:
- 10bit parallel Serdes Interface (TBI)
- 8bit GMII with rate control to MAC
- Target Technologies:
- Altera - Cyclone-II..V / Arria (any) / Stratix (any)
- Xilinx - Spartan 6,7 / Virtex (any) / Kintex (any)
- 0.09um and below standard cell ASIC
Block Diagram of the 10/100/1000 SGMII PCS Core