The PE-MACMII (TM)provides a 10/100 Mbps Ethernet Media Access Controller (MAC) for incorporation in a customer’s own ASIC design. The PE-MACMII module consists of six sub-modules. These sub-modules comprise the transmit and receive portions of the Ethernet MAC plus three supporting sub-modules. The core is adaptable to a wide range of system requirements. For example, it is designed to interface to 10 or 100 Mbps MII-based PHY devices but the range of PHYs supported can readily be extended by adding one of the optional interface modules that are available for the core. Similarly, the core offers a processor independent 16-bit host interface but can readily be interfaced to a range of standard buses through the addition of bridges such as the optional AMBA AHB Bridge provided with the PE-MACMII core.
- Supports 10 or 100 Mbps MII-based PHY devices including: 10Base-T, 100Base-TX, 100Base-FX, and 100Base-T4
- Supports IEEE 802.3x Full Duplex Flow Control and Half Duplex Back Pressure
- Meets ISO / IEC 802.3 and IEEE 802.3u specifications
- Meets VSIA’ s specification for a soft Virtual Component
- Optional interface modules available for RMII, SMII, ENDEC (10T) and PMD (100X)
- 16-bit host interface. Optional AMBA AHB bridge supplied with core.
- Additional PE-MSTAT registerbased statistics module available
- Optimized for switching, multiport and embedded applications
- Fully synthesizable
- Scan insertion-friendly design
- Verilog source code
- Synthesis constraints files
- Functional testbench with documentation of the PE-MACMII’s conformance to appropriate IEEE PICS
- Expanded Statistics vectors for certain RMON and Etherstats applications