The Chevin Technology XGUDP is an ultra-low latency IP block which simplifies the integration of the UDP protocol into any Xilinx FPGA at rates of 10Gbit/s.
Ultra-low latency is achieved by offloading frame assembly and hardware accelerated checksum calculation for UDP datagrams.
This allows user data to take the shortest and lowest latency path to and from wire.
- Low Latency TX 38.4ns RX 38.4ns
- Small Logic Footprint 3k LUTs
- Small Memory Footprint 4 RAMB36E
- Programmable UDP Port numbers
- Integrated Streaming FIFO – 4 Block RAMs
- Integrated IP Checksum Generator/Check
- Flow Control between MAC/User logic
- Detailed traffic analysis statistics collection
- MAC interface, 64bit @ 156.25MHz
- Application interface, 64bit @ 156.25MHz
- IP blocks sold separately for flexible solutions
- Jumbo Frames; up to 9KB
- Chevin Technology’s 10G & 25G UDP Ethernet IP is FPGA Synthesisable EndPoint with Checksum Offload for ultra low-latency connectivity.
- The 10G & 25G UDP IP cores simplify FPGA integration of an ultra fast UDP/IP layer in any FPGA by handling the complete Ethernet frame assembly.
- A simple AXI4 streaming interface is all that is required to start sending and receiving UDP datagrams, and only the “user data” payload is exchanged between the application and the UDP block. For a single port application the port number can be set to a constant, hard coded or software configurable. A multi- port application is supported by a single UDP IP core by using the udp_port sideband embedded in the streaming interface.
- • Encrypted compiled netlist
- • Datasheet & User Guide to assist integration
- • Reference Designs for AlphaData boards
- ADM-PCIE-KU3, ADM-PCIE-8V3, ADM-PCIE-9V3
- • Simulation Test bench
- • Build scripts for Vivado
- • Support for integration into FPGA
- Trade execution & monitoring
- Data Storage & Capture systems
- HPC / Big Data systems
- Signal processing systems
- Data Mining
Block Diagram of the 10 & 25Gbit/s Ethernet UDP/IP Hardware Stack for FPGAs