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10 & 25Gbit/s Ethernet UDP/IP Hardware Stack for FPGAs
The Chevin Technology UDP/IP is an ultra-low latency IP core that offers fast transport layer Ethernet data transfer. Chevin Technology's UDP/IP simplifies the integration of the UDP protocol into any Xilinx FPGA at rates of 10 & 25 Gbit/s.
Ultra-low latency is achieved by offloading frame assembly and hardware accelerated checksum calculation for UDP datagrams.
This allows user data to take the shortest and lowest latency path to and from wire.
Ultra-low latency is achieved by offloading frame assembly and hardware accelerated checksum calculation for UDP datagrams.
This allows user data to take the shortest and lowest latency path to and from wire.
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Block Diagram of the 10 & 25Gbit/s Ethernet UDP/IP Hardware Stack for FPGAs
