The S3DA100K10BT40LP is a low sample rate Voltage DAC that is ideal for low frequency auxiliary applications.
The Voltage DAC is implemented using resistor-string architecture. A resistive ladder divides the reference voltage into the required steps and MOS pass gate switches select the appropriate output level. A main DAC is used in conjunction with a sub DAC to give a more favorable area resolution trade-off.
The resolution of the sub DAC and main DAC add, giving a linear area resolution trade off, as opposed to the exponentially increasing number of resistors with just one DAC. The AUXDAC_VOUT is a Single Ended voltage with a 2.0V output swing.
- 40nm TSMC Logic LP Process, 7 Metals Used
- (No Analog Options) with Deep-Nwell
- 2.5V and 1.1V Supplies
- 10 Bit DAC resolution
- Update Rate of 100KHz
- 2.0Vpp Single Ended Output Range
- < 2.3mW at 100KHz
- DNL< 1LSB Typ.; INL< 2LSB Typ.
- SNR = 60dB, ENOB=9.4bits, SFDR = 61dBc, FOUT= 30kHz
- Stand-By and Power-Down Modes
- Area Pre-shrink:0.1mm2
- The power of the DAC is inclusive of the internal reference circuitry,and is specified for a 100KHz update frequency operation driving into a 10pF and 10Kohm parallel load. This 10-bit Voltage DAC features an excellent static performance that includes ±1LSB DNL and ±1LSB INL.
- The S3DA100K10BT40LP is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- House Keeping / Auxiliary Functions
Block Diagram of the 10-Bit 100KHz Voltage DAC IP Core