The S3DA100K10DC18 is a low sample rate DAC that is ideal for low frequency and housekeeping applications.
The DAC is implemented with a resistive architecture and output buffer to drive large capacitive loads. The DAC output is a single ended voltage with a 2V output swing.
The power of the DAC is determined by the noise requirements, the load, and the maximum sample rate. Trade offs can be made on the power consumption by limiting any of these specifications. The power figure of 1 mW is quoted for the total power for 100KHz update frequency operation driving a 10pF and 10Kohm parallel load.
- 0.18um TSMC RF Process (No Analog Options)
- 3.3V Supplies
- 10 Bit DAC resolution
- Update Rate of 100KHz
- 2.0 Vpp Single Ended Output Range
- < 1mW at 100KHz
- DNL< 1LSB Typ.; INL< 1LSB Typ.
- SNR = 60dB
- Stand-By and Power-Down Modes
- Compact Die Area: 0.2mm2
- This 10-bit DAC features an excellent static performance that includes ±1LSB DNL and ±1LSB INL. The buffer can be bypassed if desired when driving an external buffer.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- Housekeeping / Auxiliary Functions
Block Diagram of the 10-Bit 100KHz Voltage DAC IP Core