This IP consists of an ultra-low power ADC with compact die area available on 65 nm CMOS tech-nology. The ADC performs 10-Bit resolution conversion at 100 KS/s and consumes 500 nW (ADC+Converter) at 1 KHz input frequency with analog power supply of 0.5 V.
The ADC contains a clock generator block and there is no need of external clock signal. READY signal is the external sampling signal and controls the conversion procedure. Sampling block requires 1.2 V voltage signal to drive its switches. The converter block can generate this voltage internally or an external supply (VDDsw pin) can feed the sampling block.
SAR architecture is employed in this ADC in order to use the benefits of technology shrinking. In other words, size and power consumption of the block can be reduced by technology scaling in this structure.