10-Bit 100kS/s Voltage DAC - TSMC 0.18um
The Voltage DAC is implemented using resistor-string architecture. A resistive ladder divides the reference voltage into the required steps and MOS pass gate switches select the appropriate output level. A main DAC is used in conjunction with a sub DAC to give a more favorable area resolution trade-off. The resolution of the sub DAC and main DAC add, giving a linear area resolution trade off, as opposed to the exponentially increasing number of resistors with just one DAC. The AOUT is a Single Ended voltage with a 2.3V output swing.
The power of the Voltage DAC is determined by the noise requirements, the load, and the maximum sample rate. Trade-offs can be made on the power consumption by limiting any of these specifications.
This 10-bit Voltage DAC features an excellent static performance that includes ±1LSB DNL and ±1LSB INL. The S3DA100K10BT18 is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
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Block Diagram of the 10-Bit 100kS/s Voltage DAC - TSMC 0.18um
