10-bit 1MS/s Dual-Channel SAR ADC

Features

• TSMC 65nm Logic Low-Power Process
• 7 Metals (5 thin metals)
• No Analog Options
• 2.2V & 1.2V Supplies
• 10-bit Dual-Channel SAR ADC
• Sampling Rate: 1MS/s
• Input Clock Frequency: 12MHz
• Fully-Differential or Pseudo-Differential Unipolar Input Programmable Modes:
• 1.5Vppdiff Input Range (Diff. Mode)
• 1.5Vpp Input Range (Pseudo-Diff. Unip. Mode)
• Input Capacitance: 0.7pF
• External Reference VBG=1.5V
• Gain Error < 1%
• Input Referred Offset < 1%
• Reference Buffer Included
• Outstanding Static Performance:
• DNL = ±0.9 LSB
• INL = ±1.5 LSB
• No Missing-Codes
• Outstanding Dynamic Performance:
• 63.0dB SFDR
• 56.0dB SNR
• 8.9-bit ENOB
• [Noise integrated up-to Nyquist]
• Standby and Power-Down Modes
• Low Power Dissipation:
• 1.3mW (Dual-Channel ADC + Ref. Buffer)
• Compact Die Area:
• 0.09mm2 (Dual-Channel ADC + Ref. Buffer)

Benefits

• For application flexibility, this IP includes a Reference Buffer to drive the ADCs capacitance, while keeping a high-impedance interface to the external Voltage Reference.
• This 10-bit Dual-Channel ADC features an outstanding dynamic performance that includes 63.0dB SFDR, 56.0dB SNR and 8.9-bit ENOB (noise integrated up-to Nyquist). The static performance includes ±1.5LSB INL and ±0.9LSB DNL with No Missing-Codes.
• The S3ADSIQ1M10BT65LP does not require any special analog options and can be cost-effectively ported across foundries and process nodes upon request.

Deliverables

• Datasheet
• Characterization Report
• Flat Netlist (cdl)
• Layout View (gds2)
• Abstract View (lef)
• Timing View (lib)
• Behavioral Model (Verilog)
• Integration Support

Applications

• Motion and Environmental Sensing
• Industrial Control
• Auxiliary Control
• General Purpose Acquisition

Block Diagram of the 10-bit 1MS/s Dual-Channel SAR ADC

• see the entire 10-bit 1MS/s Dual-Channel SAR ADC datasheet
• get in contact with 10-bit 1MS/s Dual-Channel SAR ADC Supplier