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10-Bit, 20/85/100/240 MSPS 3.3V/1.8V CMOS Video DAC
The KTDA10240 is a 3-channel 10-bit monolithic digital-to-analog video converter (DAC) with a differential-to-single-ended output stage that is capable of driving 75Ù coaxial cable. The DAC can also output differential signal directly. The DAC operates at various conversion rates up to 240MSPS, with outstanding dynamic performance up to Nyquist frequencies.
The DAC core requires 3.3V analog supply and 1.8V digital supply and consumes less than 200mA at 240MSPS with on-chip bandgap reference.
The DAC is fabricated on a number of TSMC-compatible and other general 0.18um CMOS processes in leading foundries including SMIC, Jazz and HHNEC.
The test chips are available in both 48-pin TQFP and 44-pin PLCC. Only 2 channels of the DAC are included on the test chips due to package limitation. Evaluation boards are available.
The DAC core requires 3.3V analog supply and 1.8V digital supply and consumes less than 200mA at 240MSPS with on-chip bandgap reference.
The DAC is fabricated on a number of TSMC-compatible and other general 0.18um CMOS processes in leading foundries including SMIC, Jazz and HHNEC.
The test chips are available in both 48-pin TQFP and 44-pin PLCC. Only 2 channels of the DAC are included on the test chips due to package limitation. Evaluation boards are available.
Features
- Low 3.3V analog core supply
- 1.8V digital logic supply
- ENOB = 10 bit to 100MSPS
- SFDR > 73dBc
- 3-channel with integrated bandgap
- Integrated line driving capability: directly drive 75Ù coaxial cable, up to 34mA output current per channel
- Output method: Single-ended or differential
- Flexible process options: multiple versions to fit both logic and analog processes
- Available and silicon-proven in Jazz, SMIC, HHNEC and in TSMC compatible 0.18um CMOS
Benefits
- High-performance
- 10 ENOB with full-scale input at 100MSPS.
- Built-in line driver
- Single-ended and differential line diver.
- Flexible foundry/process options
- Fabricated and verified in both TSMC compatible and non-compatible 0.18um CMOS processes with and without analog/RF options.
Deliverables
- High-level behavioral model (AHDL)
- Pin file (.LEF)
- GDSII
- Flat netlist
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