The S3TD250M10BGF28SLP Triple-DAC employs a current steering architecture with differential current outputs. It uses 5 linear bits and 5 binary bits, all of which are generated from within the current source array. The circuit is a current output DAC designed to be loaded by either single or double terminated 75 Ohm Lines.
The Triple-DAC segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency
- Globalfoundries 28nm SLP Process, 7 Metals Used
- 1.8V and 1.0V Supplies.
- Triple Channel VDAC which is easily configurable as single VDAC or as 6 channel VDAC due to flexible layout
- Sense comparator in each channel for load detection
- 6-bit Gain Control
- Single-Ended or Differential Output Range
- Full scale output currents of 9mA to 26.66mA
- Current Consumption:
- DNL< 1LSB; INL< 1.0LSB Typ.
- SFDR=55dB @250MS/s,FOUT=1MHz,Vo=0.7VPP Typ.
- Stand-By and Power-Down Modes
- Total Die Area pre-shrink (with biasing circuitry): 0.262mm2
- This 10-bit DAC features an excellent static performance that includes ±1LSB DNL and ±1.0LSB INL.
- The gain of the DAC is 4-bit controllable over a range from - 9.3dB to 7.22dB. This is achieved with integrated bias current circuitry.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- Subject to Agreement
- Composite Video
- RGB Video
Block Diagram of the 10-Bit 250MS/s Triple Current Steering DAC