The S3DA300M10BT28 employs a current steering architecture with differential current outputs. It uses 5 linear bits and 5 binary bits, all of which are generated from within the current source array.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
- 28nm TSMC HPC Process, 6 Metals Used
- 2.5V Supply
- Sampling Rate up to 300MS/s
- 1.0Vpp Differential Output Range
- DNL< 1.0LSB; INL<2.0LSB.
- Excellent Dynamic Range at 300MS/s
- 57dBFS SNR @ Fout=10MHz
- 65dBc SFDR @ Fout=10MHz
- 8.8bits ENOB @ Fout=10MHz
- Internal 0.9V Regulator
- Stand-By and Power-Down Modes
- Die Area pre-shrink: 0.07mm2
- This 10-bit DAC features an excellent static performance that includes ±0.8LSB DNL and ±1.5LSB INL for typical conditions.
- Dynamic performance highlights considering a signal frequency of 10MHz and 300MS/s conversion rate include an SNR=57dB and an SFDR=65dBc.
- The S3DA300M10BT28 is designed for operation up to 300MS/s. The S3DA300M10BT28 is designed in a 28nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (VHDL/Verilog)
- Integration Support
- WiFi 802.11xx, WiMAX 802.16x
- Wireline communications
- Direct Digital Synthesis
Block Diagram of the 10-Bit 300MS/s Current Steering DAC