The 10-bit 300MS/s Quad DAC employs a current steering architecture with differential current outputs. It uses 5 linear bits and 5 binary bits, all of which are generated from within the current source array. The circuit is a current output DAC designed to be loaded by double terminated 75 Ohm Lines.
The Quadruple-DAC segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
This 10-bit DAC features an excellent static performance that includes ±1LSB DNL and ±2LSB INL.
The gain of the DAC is 6-bit controllable over a range from -8dB to 0dB. This is achieved with integrated bias current circuitry.
The 10-bit 300MS/s Quad DAC is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- 55nm TSMC Logic LP Process, 7 Metals Used
- No Analog Options
- 3.3V and 1.2V Supplies
- Quadruple Channel DAC which is Easily Configurable as a Single VDAC Due to Flexible Layout
- Sampling Rate up to 300MS/s
- 6-bit Gain Control
- Sense Comparator in Each Channel
- Single-Ended or Differential Output Range
- Full Scale Output Currents 17mA to 34mA
- 93mA @IFS=19mA
- 156mA @IFS=34mA
- DNL< 1LSB Typ.
- INL< 2LSB Typ.
- SFDR>53dBc at 300MS/s, Fout= 1MHz
- Max Output Swing 1.3V Single-ended
- Small Die Area
- Composite Video
- RGB Video
Block Diagram of the 10-bit 300MS/s Quad DAC - TSMC 55nm