The 10-bit 4-channel 100 MSPS ADC employs a high-performance front-end sample-and-hold with differential multi-stage pipelined architecture and output error correction logic. The reference generator, current source and LVDS receiver are also included to provide a complete ADC. The ADC operates with sampling rate up to 100 MSPS and a corresponding input clock up to 200 MHz (input clock is divided by two). The ADC can be configured to achieve addition power saving at low sampling rate, supports standby mode and features the excellent dynamic and static performance, wide bandwidth inputs, low power consumption and compact die area.
The block is designed on TSMC CMOS 65 nm technology.