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Voltage Domain Interfacing Cells for use between power domains using core transistors.
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10 Bit 40 MSPS Pipeline ADC
This customizable ADC has been designed to reduce time to market, risk and cost in the development of analog front-ends. A range of supporting IP blocks such as PLL's and reference circuits as well as companion IP blocks such as D/A converters are also available.
The ADC has a fully differential pipeline architecture in order to maximise dynamic range and noise immunity. Digital correction of the 9 MSB bits ensures good linearity approaching Nyquist.
The ADC has a fully differential pipeline architecture in order to maximise dynamic range and noise immunity. Digital correction of the 9 MSB bits ensures good linearity approaching Nyquist.
Features
- 1.8V power supply in 0.18um CMOS process
- Input range of 1.5 Vp-p Differential
- Dynamic Performance
- 56dB SNR at Fin=10MHz
- 65dB SFDR at Fin=10MHz
- DNL 0.75 LSB
- INL 1 LSB
- Die area of 1.1mm2
- Power Dissipation < 55mW
- Scalable to Lower Resolutions
Benefits
- Part of a family of mixed signal blocks enabling it to be used as part of an analog front end.
- Area of 1.1mm2 including reference circuits.
- Developed on standard 0.18um process, which is ideal for integration with a DSP engine.
- Does not require special analog processing options.
- It has low distortion and high dynamic range so can be used in a number of demanding applications.
- Readily portable across foundries.
- Operating at 40MSPS, the ADC consumes only 55mW.
- Analog bandwidth of 55MHz.
Deliverables
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (tlf)
- Behavioral Model (VHDL/Verilog)
- Silicon Samples
- DemonstrationEvaluation Board
- Integration Support
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