The 10-bit 40MS/s IQ ADC is silicon proven in TSMC 65nm, it employs a high-performance dual input sample-and-hold (S/H) circuit together with a differential pipeline architecture and digital error correction.
The dual input architecture enables this single ADC to be used as a complete IQ ADC solution. In this configuration, both S/H circuits are used and the single ADC core converts each channel alternately, thereby enabling very high channel-to-channel matching and minimum die area in IQ applications.
This 10-bit ADC features an excellent static performance that includes ±0.5LSB DNL and ±1.0LSB INL typ. Dynamic performance highlights include SNR of 56.5dB, SFDR of 66dB and SNDR of 56dB, yielding 9.0ENOB performance.
Auxiliary circuits comprising a bandgap, current biasing and internal reference buffers are also included. The 10-bit 40MS/s IQ ADC does not require any special analog options, and can be cost-effectively ported across foundries and process nodes upon request.