Ridgetop Group’s 10-bit, 4 MS/s ADC core utilizes a pipeline architecture in the TSMC 0.25 μm process. The ADC converter design is 10-bit 4 MS/s, as shown in Figure 1.
The cell incorporates a 10-bit pipeline analogto- digital converter with up to five samplehold blocks. Four sample-hold blocks are used in parallel to sample input voltage and current. The fifth sample-hold block is used with the input multiplexer to provide up to eight auxiliary inputs. The cell also includes a current-to-voltage converter that converts current input signals to voltages.
- 10 bits of resolution
- 4 MS/s sampling rate
- TSMC 0.25 μm mixed-signal process (retargetable)
- 3.0 to 3.6 V analog supply voltage
- 2.25 to 2.75 V digital supply voltage
- Area 1.25 x 1.5 mm (TSMC 0.25 μm process)
- Pin provided for enable mode
- External (or internal) reference voltage
- Up to 10 analog inputs
- MIM capacitors
- Pipeline architecture
- Includes complimentary license of patented PDKChek® die-level process monitor yield improvement solution