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10-Bit, 50/100/200/250 MSPS 1.8V CMOS ADC
The KTAD10200 is a 10-bit monolithic sampling analog-to-digital converter (ADC) with a fully-differential wideband on-chip track-and-hold circuit that is capable of preserving high quality input signals beyond the Nyquist frequency. The ADC operates at various conversion rates up to 250MSPS in a fully integrated environment, with outstanding dynamic performance over a wide bandwidth up to 400MHz.
The ADC core requires a single 1.8V power supply and consumes less than 60mW at 200MSPS with on-chip CMOS output data drivers.
The ADC is fabricated on a number of TSMC-compatible and other general 0.18um CMOS processes in leading foundries including SMIC, Jazz and HHNEC.
The test chips are available in both 48-pin TQFP and 44-pin PLCC. The test chips support up to 170MSPS in CMOS mode using on-chip CMOS data and clock drivers. Evaluation boards are available.
The ADC core requires a single 1.8V power supply and consumes less than 60mW at 200MSPS with on-chip CMOS output data drivers.
The ADC is fabricated on a number of TSMC-compatible and other general 0.18um CMOS processes in leading foundries including SMIC, Jazz and HHNEC.
The test chips are available in both 48-pin TQFP and 44-pin PLCC. The test chips support up to 170MSPS in CMOS mode using on-chip CMOS data and clock drivers. Evaluation boards are available.
Features
- 1.8V core supply (1.6V to 2V operation)
- ENOB = 8.5 bit to 400MHz
- SFDR = 57dBc to 245MHz
- Linearity:
- DNL: ±0.6 LSB
- INL: ±1.1 LSB
- Ultra-low power ADC core 60mW at 200MSPS
- Differential input with >400MHz bandwidth
- On-chip track-and-hold
- Flexible analog input: 1Vp-p to 1.5Vp-p
- Flexible process options: multiple versions to fit both logic and analog processes
- Available and silicon-proven in Jazz, SMIC, HHNEC and in TSMC compatible 0.18um CMOS
Benefits
- High-performance 8.5 ENOB with full-scale input @ 165MHz using noisy CMOS data driver at 100MSPS.
- Low power Consumes less than 60mW @ 200MSPS.
- Flexible foundry/process options Fabricated and verified in both TSMC compatible and non-compatible 0.18um CMOS processes with and without analog/RF options
Deliverables
- High-level behavioral model (AHDL)
- Pin file (.LEF)
- GDSII
- Flat netlist
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