The A10B500M is an ultra-low-power and high-speed analog to digital converter (ADC) intellectual property (IP) design block. It is a successive approximation register (SAR) ADC, with 10-bit resolution and a sampling rate of 500 megasamples per second (MSPS).
The A10B500M delivers performance that is unrivaled in the ultra-low power ADC market, with a power consumption of only 1.2 mW, and input bandwidth of 3 GHz.
The cost-effective IP block has been designed and verified for FDSOI processes and validated at 28 nm FDSOI process.
The ADC IP is also available in a radiation-tolerant version, that can function under harsh environmental constraints.