10 Bit 60 MSPS Pipeline ADC in 0.18u (CMOS Imaging Applications)

Features

• 0.18µm 4 metal CMOS with MiM option
• 1.8V power supply
• Input range of 1.5 Vp-p differential
• Dynamic Performance
• SNR: 56dB minimum
• Black to white transition: 1 pixel
• DNL < 0.5 LSB
• INL < 3 LSB
• Power/Sample Rate Programmability
• 65mW @60 MSPS
• 32mW @30 MSPS
• Standby power consumption 300µW
• Sleep mode power consumption: 1µW
• Die area of 0.5mm2
• Scan test for digital decoder

Benefits

• Part of a family of mixed signal blocks enabling it to be used as part of an analog front end.
• Area of 0.5mm2 including reference circuits.
• Developed on 0.18mm 4 metal CMOS process with MiM option.
• The ADC has excellent linearity and SNR performance making it ideal for CMOS imaging applications.
• Operating at 60MSPS, the ADC consumes only 65mW.
• A number of low power modes available for lower sampling rates
• Standby mode power consumption of 300uW
• Power down mode
• Readily portable across foundries.

Deliverables

• Datasheet
• Characterization Report
• Flat Netlist (cdl)
• Layout View (gds2)
• Abstract View (lef)
• Timing View (tlf)
• Behavioral Model (VHDL/Verilog)
• Silicon Samples
• DemonstrationEvaluation Board
• Integration Support

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