This ADC has been designed to reduce time to market, risk and cost in the development of analog front-ends. This dual channel ADC accepts an 80MHz input clock to operate at 80Ms/s per channel. It uses the 2 ADC cores with shared references and timing to ensure excellent matching performance.
The ADC has a pipeline architecture with differential input in order to maximize dynamic range and noise immunity. Digital correction of the 9 MSB bits ensures good linearity approaching Nyquist.
An analog test input signal port allows the normal
input to be bypassed for direct ADC testing. A scan test port is available for testing of the digital circuitry
The design does not require any special analog
options using the baseline digital CMOS process
which means it is highly portable between foundries.
The integrated clamp circuit allows the signal to be AC coupled to the ADC. Alternatively, this clamp circuit can be powered down separately allowing DC coupling of the input signal.
- 90nm 6 Metal CMOS (No analog options)
- 1.2V power supply
- 1 Vpp differential input range
- Dual 80MSPS operation
- Dynamic performance
- 56dB SINAD at fIN=20MHz
- 68dB SFDR at fIN=20MHz
- DNL 0.5 LSB
- INL 1 LSB
- Total Die area of 0.66mm2
- Power/sample rate scalability
- 65mW at 80 MSPS
- 35mW at 40 MSPS
- Stand-by and power down modes
- Analog test input signal port
- Scan test for digital section
- The area of the ADC is 0.66mm2 including reference circuits.
- Operating at 80MSPS, the dual channel ADC consumes only 65mW.
- The design also operates at 40MPS, with a power consumption of 35mW.
- The dual channel ADC has been developed on 90nm LP process, which is ideal for handheld devices.
- Does not require special analog processing options.
- It has low distortion and high dynamic range so can be used in a number of demanding applications.
- The circuit has a minimum full power analog bandwidth of 80MHz.
- The ADC is readily portable across foundries.
- Readily portable across foundries.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (tlf)
- Behavioral Model (VHDL/Verilog)
- Silicon Samples
- DemonstrationEvaluation Board
- Integration Support