10 Bit 80 MSPS Pipeline ADC

Features

• 90nm 6 Metal CMOS process (No analog options)
• 1.2V power supply
• 1Vp-p Differential Input Range
• Dynamic Performance
• 59dB SINAD at Fin=10MHz
• 65dB SFDR at Fin=10MHz
• DNL < 0.5 LSB
• INL < 1 LSB
• Die area of 0.38mm2
• Power/sample rate scalability
• 36mW @ 80 MSPS
• 10mW @ 20 MSPS
• Standby and power down modes of operation
• Analog test input Signal port
• Scan test for digital section

Benefits

• Total area of 0.38mm2 including reference circuits.
• Operating at 80MSPS, the ADC consumes only 36mW.
• The ADC power consumption/sample rate can be reduced in 4 steps to a minimum of 10mW at 20MSPS
• Developed on standard 90nm process, which is ideal for integration with a DSP engine.
• Does not require special analog processing options.
• It has low distortion and high dynamic range so can be used in a number of demanding applications.
• Readily portable across foundries.
• Analog bandwidth of 100MHz.

Deliverables

• � Datasheet
• � Characterization Report
• � Flat Netlist (cdl)
• � Layout View (gds2)
• � Abstract View (lef)
• � Timing View (tlf)
• � Behavioral Model (VHDL/Verilog)
• � Silicon Samples
• � DemonstrationEvaluation Board
• � Integration Support