This ADC has been designed to reduce time to market, risk and cost in the development of analog front-ends. This ADC accepts an 80MHz input clock to operate at 80Ms/s per channel.
The ADC has a pipeline architecture with differential input in order to maximize dynamic range and noise immunity. Digital correction of the 9 MSB bits ensures good linearity approaching Nyquist.
An analog test input signal port allows the normal
input to be bypassed for direct ADC testing. A scan test port is available for testing of the digital circuitry
The design does not require any special analog
options using the baseline digital CMOS process.
The integrated clamp circuit allows the signal to be AC coupled to the ADC. Alternatively, this clamp circuit can be powered down separately allowing DC coupling of the input signal.