10-bit 80MS/s Octa-Core Ultra-low power SAR ADC

Features

• GF 28nm SLP Process
• No Analog Options
• 1.0V & 1.8V Supplies
• 10-bit SAR ADC
• 4 I/Q-pair ADC Channels: Total 8 ADC Cores
• 80MS/s Sampling Rate per ADC Core
• Internal Reference Buffers for 1.0V VREF
• Differential Input Signal Range: 1.0Vppdiff
• Static Performance:
• DNL < ± 0.9 LSB (no Missing-Codes)
• INL < ± 1.5 LSB
• Dynamic Performance:
• -66.0dB THD
• 56.5dB SNR
• 9.0-bit ENOB
• [Noise integrated up-to Nyquist]
• Standby and Power-Down Modes
• Ultra-Low Power Dissipation: 20mW
• 8 Cores Converting Simultaneously
• Including References Buffers for 8 ADCs
• Ultra-Compact Die Area: 0.2mm2

Benefits

• This IP includes 4 I/Q-pair ADC Channels with each one of the 8 Cores sampling at 80MS/s. It features an excellent dynamic performance including -66.0dB THD and 9.0-bit ENOB, while dissipating a mere 20mW for the complete 8 ADC Cores.
• The S3ADS4IQ80M10BGF28SLP can be cost-effectively ported across foundries and process nodes upon request.

Deliverables

• Datasheet
• Characterization Report
• Flat Netlist (cdl)
• Layout View (gds2)
• Abstract View (lef)
• Timing View (lib)
• Behavioural Model (Verilog .v)
• Integration Guidelines and Support

Applications

• Connected Consumer Devices
• LTE
• IOT
• DVB
• Home Network
• Wireless & Wireline Communications
• Imaging

Block Diagram of the 10-bit 80MS/s Octa-Core Ultra-low power SAR ADC

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