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10-Bit, 833/1100 MSPS 1.0V/1.8V CMOS DAC
The KTDA10800 is a low-power high-performance 10-bit digital-to-analog converter (DAC) fully integrated in TSMC 90nm CMOS process. The DAC operates at various conversion rates up to 1.1GSPS with outstanding dynamic performance over a wide bandwidth. Even with clock jitter and other test setup limitations, 72dB SFDR / 9.2ENOB and 61dB SFDR / 8.2 ENOB is measured at 800MSPS with full-scale 41.3 MHz and 193.2 MHz sine wave inputs, respectively. Better than 68dB SFDR is preserved with full-scale 54.3MHz sine wave at 1.05 GSPS. KTDA10800 exceeds all IEEE802.3an specifications for 10GE copper transceiver.
The DAC core requires dual 1.0V/1.8V power supply and consumes 49mW at 800MSPS, the lowest reported in the industry.
Unlike other high-speed DACs at this performance level which requires 10’s or even 100’s of supply/ground pins and expensive low-inductance packages, KTDA10800 only requires total 5 supply and ground pins and can sustain 2.5nH on each pin.
The DAC is fabricated and verified in TSMC 90nm 1-Poly-9-Metal CMOS processes. The core occupies merely 0.36mm2 die area.
The DAC core requires dual 1.0V/1.8V power supply and consumes 49mW at 800MSPS, the lowest reported in the industry.
Unlike other high-speed DACs at this performance level which requires 10’s or even 100’s of supply/ground pins and expensive low-inductance packages, KTDA10800 only requires total 5 supply and ground pins and can sustain 2.5nH on each pin.
The DAC is fabricated and verified in TSMC 90nm 1-Poly-9-Metal CMOS processes. The core occupies merely 0.36mm2 die area.
Features
- Supply: 1.1V/1.8V
- Reduced GND/Supply pins: 5 supply/GND pins
- Low cost package: sustains up to 2.5nH package inductance per pin
- ENOB: >9.2 bit @ 41MHz, > 8.2 bit @ 193MHz (limited by clock jitter in test setup)
- SFDR: 72dBc @ 41MHz, 61dBc @ 193MHz
- Ultra-low power DAC core 49mW at 800MSPS
- Exceeds IEEE 802.3an specifications
- Silicon-proven in TSMC 1P9M 90nm CMOS process
Benefits
- High-performance
- 9.2 ENOB and 72dB SFDR with full-scale input @ 800MSPS.
- Ultra-low power
- Consumes merely 49mW @ 800MSPS.
- Relaxed packaging and integration requirements
- 2.5nH inductance and 5 power and GND pins
- Fabricated and verified in TSMC 90nm CMOS processes.
Deliverables
- High-level behavioral model (AHDL)
- Interface timing model (.lib)
- Pin file (.LEF)
- GDSII
- Flat netlist
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