The 10-bit 8MS/s ADC IP is designed to digitize 16 different single-ended inputs and dissipating only 10mW.
The single-ended inputs have a dynamic range of 2.5V. A sample-and-hold with a single-ended to differential conversion is used such that the ADC core digitizes a fully-differential signal.
This 10-bit ADC features an excellent static performance that includes ±0.5LSB DNL and ±1.0LSB INL. Dynamic performance highlights considering an input signal with 40kHz frequency and 8MS/s sampling rate include an SNR of 57dB and 9.0-bit ENOB.
Auxiliary circuits comprising current biasing and voltage reference buffers with internal decoupling are also included to provide a complete ADC solution.
The 10-bit 8MS/s ADC with 16:1 Input MUX can be cost-effectively ported across foundries and process nodes upon request.
- 65nm TSMC Logic LP Process
- No Analog Options
- Dual 2.5V and 1.2V Supply
- Sampling Rate of up to 8MS/s
- 2.5Vpp Input Range
- Low-Power Dissipation:
- DNL= ±0.5LSB Typ.; INL= ±1.0LSB Typ.
- SNR= 57dB
- 9.0-bit ENOB
- Stand-By, Sleep and Power-Down Modes
- Compact Die Area
Block Diagram of the 10-bit 8MS/s ADC with 16:1 Input MUX - TSMC 65nm LP