The ADC is a high speed analog-to-digital converter specified to operate from a nominal 1.2V analog supply and 1.2V digital supply. To achieve lower power dissipation, a proprietary I/Q opamp sharing architecture is employed. In addition, multiple (4) radix MDAC is adopted for the best combination of speed, power and performance optimization. By implementing pipelined architecture with alignment and output error correction logic, the ADC offers accurate performance and guarantees no missing codes over the full operating temperature range.
The ADC has no external pin requirements except analog input and power supply, and it includes an internal bandgap biasing block, a digital clock management unit, and an output buffer with 12bit unsigned binary digital outputs. All digital interface signals are 1.2V based, providing customers flexibility to directly integrate into design core.
The ADC is compact and occupies layout area of 0.56mm2 in 55nm logic CMOS process without any mixed mode options. The fully differential architecture makes it insensitive to substrate noise coupling. Thus it is ideal as a mixed signal ASIC macro cell. The ADC can be placed into a power down standby mode of operation reducing power to below 70uW.
- 1.55nm LL CMOS logic process without any mixed mode options. 2.Single 1.2V power supply required.
- 3.I/Q opamp sharing architecture for lower power dissipation and small die size.
- 4. Fully integrated internal reference generator with no external pins.
- 5. 12-bit resolution pipelined analog-to-digital converter.
- 6.Maximum differential input of 1.1Vdpp.
- 7. Input clock frequency of up to 200MHz.
- 8. Dual-channel concurrent sampling @ 100Msps.
- 9.Power consumption of 65mW @ 100Msps dual channel operation.
- 10. Core layout area of 0.56mm2 (before shrink) with internal bandgap and reference.
- 11. No MIM option necessary with logic process MOM capacitors.
- 12. No external pins required except analog inputs and one-pair of analog power supply/ground.
- 1. Internal reference
- 2. Compact Die Area
- 2.Flat Netlist (cdl)
- 3.Layout View (gds2)
- 4.Abstract View (lef)
- 5.Timing View (lib)
- 6.Behavioral Model (Verilog)