10 Gb/s Ethernet MAC

Features

• In-band START(/S/) and TERMINATE(/T/) control character insertion
• Preamble/Start-of-Frame Delimiter Insertion
• Option to replace MACD, MACS, ETHERTYPE and VLAN/PRI fields in the transmitted frame with values from registers
• Frame Check Sequence(FCS) computation/insertion and extraction/checking
• Frame Transmit Error Propagation
• Frame delineation using control characters, preamble/SFD in the ingress direction
• Handling different kinds of errors and recovery
• Inter Frame Gap(IFG) that meets Deficit Idle Count rules
• Insertion of additional IDLEs to meet WAN-PHY rate limit
• Reconciliation sub-layer(RS) implementation including Local Fault/Remote Fault handling
• Simple System-side interface
• SDR line-side interface or option to use DDR XGMII interface
• MDIO STA for management of PHYs
• Generic CPU interface for access to Control and Status registers
• Flow-control handling in both transmit and receive directions
• Comprehensive statistics vectors and optional statistics counter block

Benefits

• Low Gate Count
• Flexible Design
• Designed for Reuse & Testability
• Proven Design Methodology
• Customization Options

Deliverables

• Functional Specification
• RTL Database
• Functional Verification Environment
• Synthesis Scripts
• Timing Report
• User Guide

Block Diagram of the 10 Gb/s Ethernet MAC IP Core

• see the entire 10 Gb/s Ethernet MAC datasheet
• get in contact with 10 Gb/s Ethernet MAC Supplier