Amidst a rich a-la-carte offering, shCODlp-100.02 is an optimized and complete configuration around high performance DAC and ADC cores which provide a higher SNR for the smallest silicon area.
Fabless companies targeting high fabrication volume would benefits from shCODlp-100.02 optimization for 0.11 um optically shrunk processes.
- Maximized yield with the best trade-off between silicon area and SoC / PCB costs
- Capacitor-less headphone driver
- Filter-less line-out
- PLL-less feature to avoid jitter noise issues
- Single master clock generates all sampling frequencies
Block Diagram of the 100 dB of SNR, 24-bit stereo audio CODEC with headphone driver and digital mixer