100 Gbit/s IEEE 802.3bj RS Encoder and Decoder
Features
- Compliant with IEEE 802.3bj, Clause 91
- Support for KR4 (528, 514) and KP4 (544, 514) Reed-Solomon (RS) code
- Corrects up to seven (KR4) or up to 15 (KP4) erroneous symbols.
Benefits
- High-throughput, low-latency core.
- Support for single channel mode (up to 100 Gbit/s).
- Support for bypass mode with low latency.
- Symbol error measurement per lane.
- Detection of un-correctable code words.
- Block-to-block on-the-fly switching between KP4/KR4 codes.
- Easy-to-use handshaking interfaces.
- No internal RAM required.
- Available for ASIC and FPGAs (Xilinx, Intel).
- Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model.
Deliverables
- Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model.
Applications
- 100 Gbit/s Ethernet over backplane
- Applications with highest throughput requirements
Block Diagram of the 100 Gbit/s IEEE 802.3bj RS Encoder and Decoder

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