IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic. The standard meets the need for higher data rates over backplanes and copper cables for 100 Gbit/s throughput. The Creonic IP cores are the ideal solution for throughputs beyond 10 Gbit/s for FPGA devices and throughputs of up to 100 Gbit/s on state-of-the-art ASIC technologies.
- Compliant with IEEE 802.3bj, Clause 91
- Support for (528, 514) Reed-Solomon (RS) code
- Corrects up to seven erroneous symbols.
- High-throughput, low-latency core.
- Support for single channel mode (up to 100 Gbit/s).
- Support for bypass mode with low latency.
- Symbol error measurement per lane.
- Detection of uncorrectable code words.
- Ease-to-use handshaking interfaces.
- No internal RAM required.
- Available for ASIC and FPGAs (Xilinx, Altera).
- Deliverable includes Verilog source code or synthesized netlist, VHDL or SystemC testbench, and bit-accurate Matlab, C or C++ simulation model.
- 100 Gbit/s Ethernet over backplane
- Applications with highest throughput requirements
Block Diagram of the 100 Gbit/s IEEE 802.3bj RS Encoder and Decoder