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100-Gbps Ultra-Low Latency Ethernet MAC & PCS (100GBASE-R4, 100GBASE-R10)
The Ultra-Low Latency Ethernet MAC and PCS is the ideal core for latency critical applications.
These IP cores are designed to minimize congestion, to eliminate high fan-out nets, and to reduce the number of pipeline stages required to a theoretical minimum.
The cores are highly scalable and can easily be customized to target any speed, technologies and process nodes.
The Ultra-Low Latency Ethernet MAC and PCS is the industry leading solution for latency critical Ethernet applications such as high-frequency trading and data center Ethernet switches.
The core is designed using advanced techniques leading to unmatched, ultra-low gate count utilization and amazing latency performances.
The IP core can be generated to operate at 10-, 25-, 40- or 100-Gbps line rate.
These IP cores are designed to minimize congestion, to eliminate high fan-out nets, and to reduce the number of pipeline stages required to a theoretical minimum.
The cores are highly scalable and can easily be customized to target any speed, technologies and process nodes.
The Ultra-Low Latency Ethernet MAC and PCS is the industry leading solution for latency critical Ethernet applications such as high-frequency trading and data center Ethernet switches.
The core is designed using advanced techniques leading to unmatched, ultra-low gate count utilization and amazing latency performances.
The IP core can be generated to operate at 10-, 25-, 40- or 100-Gbps line rate.
Features
- Compliant with the IEEE 802.3-2012 High Speed Ethernet Standard
- Ethernet MAC supports the 10GbE, 25GbE, 40GbE, and 100GbE line rate with a flexible and configurable feature set
- Highly optimized implementation resulting in ultra-low latency and very low gate count
- Soft PCS logic interfacing to standard serial transceivers at 10.3125Gbps and 25.78125Gbps
- Standard 10GbE SFI, XFI external interface operating at 10.3125Gbps
- Standard 40GbE XLAUI or 100GbE CAUI external interface consisting of serial transceiver lanes operating at 10.3125Gbps, or the CAUI-4 external interface consisting of four serial transceiver lanes operating at 25.78125Gbps.
- Pre-standard 25GbE external interface consisting of one serial transceiver running at 25.78125Gbps
- Supports 10GBASE-R and 25GBASE-R PHY based on 64B/66B encoding
- Supports 40GBASE-R4, 100GBASE-R4, and 100GBASE-R10 PHY based on 64B/66B encoding with data striping and alignment markers to align data from multiple lanes.
- Supports PCS TX to PCS RX loopback
- Supports PCS RX to PCS TX loopback
- Supports IDLE scramble test pattern for 40G and 100G with single error injection
- Supports SEEDs test pattern for 10G
- Supports block synchronization and BER monitor
- Supports multiple lanes swapping, lane alignment and deskew
- Reports lane mapping and lane skew
- Supports alignment marker programmable spacing (40G/100G)
- Supports Synchronous Ethernet (Sync-E) and multiple synchronization schemes
- Recovered clock derived from CDR is provided to the FPGA fabric
- Can also be configured with separate reference clocks for the Tx and Rx paths
- Supports timestamping (Tx, Rx)
- Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average
- Programmable IPG length (down to 1-byte)
- Programmable Maximum Receive Unit (MRU) and Maximum Transmission Unit (MTU)
- High performance configurable core data path interface at 32-bit (10G), 64-bit (25G), 128-bit (40G) and 256-bit (100G).
- Ethernet flow control and congestion management using pause frames with programmable quanta
- XON / XOFF Frame transmission can be triggered by host (software) interface or directly by core pause frame interface signals
- Programmable Tx minimum packet length with enable/disable padding option
- Programmable Rx minimum packet length
- Tx Frame Check Sequence (FCS) computation and insertion
- Programmable Tx FCS pass-through and corruption insertion modes
- Programmable Rx Preamble pass-through mode
- Programmable Tx and Rx large frame threshold detection
- Programmable Tx and Rx path VLAN detection (Programmable TPID, stacked VLAN)
- Rx Frame truncation (Frame > MRU, MII Error)
- Tx Frame truncation (Frame > MTU)
- Configurable statistics vector and collector on transmit and receive MAC data:
- Pause frames
- MII Error (RMAC)
- PCS to RMAC (Runt, Error, Drop)
- Pause Frame
- VLAN Detect
- VLAN Stack
- VLAN User Detect
- Broadcast
- Bad Frame
- Multicast
- Unicast
- FCS Error
- Frame Receive
- Frame Length
- Frame over threshold
- Frame Long
- Jabber
- Frame Short
- Segment
- Frame size histogram
- Frame ≤ 64, Frame 65-127, Frame 128-255, Frame 256-511, Frame 512-1023, Frame 1024-1518, Frame 1519-2047, Frame 2048-4095, Frame 4096-8191, Frame > 8191
- Configurable statistics vector and collector on transmit and receive PCS:
- EEE Wake Error
- Test Pattern Error (IDLE/SEED)
- Sync Header Error
- Block Error
- BIP Error (40G/100G)
- Configurable status vector and event collector on transmit and receive PCS:
- RX LPI Indication
- TX LPI Indication
- HBER
- Block Lock
- RX Fault
- TX Fault
- Align (40G/100G)
- Alignment Marker Error (40G/100G)
- Link Status
- Illegal Skew (40G/100G)
- Slip
Applications
- The Ultra-Low Latency Ethernet MAC & PCS IP cores are based on cut-through architecture and innovative FCS processing algorithms resulting in amazing latency performances. Typical applications where latency is critical:
- Data Centers and Computing
- High Frequency Trading
- Low Latency Switch
- Network Interface Card (NIC)
- HW Acceleration / Data Acquisition
- Data Mining
- Communication and Networking
- Packet Based Processing
- Core, Edge Routers
- Aggregation
- Backhaul and Access Solutions
- Line Card / Switch-Fabric Card
- Other Applications
- Ethernet Traffic Monitoring
- Test Equipment
- Low-Latency Ethernet Encryptors
Block Diagram of the 100-Gbps Ultra-Low Latency Ethernet MAC & PCS (100GBASE-R4, 100GBASE-R10)
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