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100G Interlaken Fabric Interface Core
The Xelic 100G Interlaken Fabric Interface Core (XCI4FIC) provides the flexible transport of channelized signals for both segment mode and packet mode transmission formats with configurable lane number support. Flow control is provided for both in-band and out-of-band methods with optional automatic and override insertion capability. A configurable burst scheme and scheduling enhancement is provided to optimize bandwidth throughput. The XCI4FIC contains independent Transmit and Receive processors with configurable options and a comprehensive programmable feature set. Optional loopbacks, bypass modes, counters, and programmable consequential actions are available for debug and system integration purposes. A flexible 512-bit protocol engine architecture is implemented with a data valid scheme along with a high speed system clock operating at rates up to 250 MHz. The 100G Interlaken Fabric Interface core is targeted for both ASIC and FPGA applications.
Incoming Transmit Processor signals are received through a configurable client side packet interface with indicators provided for channel identifier, start of packet (SOP), end of packet (EOP), bytes valid, and data valid. Programmable burst control settings are provided for burst min, burst max, and burst short configurations. Channel data arrives and is processed before being placed into a channel FIFO where it is extracted as required by the XCI4FIC protocol engine. The protocol engine provides the insertion of idle/burst control words, scheduling, and lane striping functions using a configurable number of high speed lane processors/interfaces. Automatic or override flow control is provided for configurable in-band or out-of-band insertion. Each transmit high speed lane processor performs 64B/67B encoding, lane meta-frame insertion, and disparity operations. Lane diagnostics are provided including status and CRC-32 protection. Optional skip word insertion is provided for clock compensation purposes. A programmable lane test pattern generator is available for diagnostics and debug.
The Receive Processor accepts independent data on a configurable number of lanes. Each lane processor performs disparity operations, lane alignment/ deskew, and 64B/67B decoding. Receive Per-Lane state machines are provided for CDR lock, 64B/67B word boundary lock, and scrambler synchronization with programmable consequential action control. Lane status information is extracted and made available through the register interface provided. A variety of interrupts are reported to indicate status of incoming lane data. Lane test pattern checkers with pattern detection capability are provided for diagnostic and debug purposes. The receive processor protocol engine performs lane de-striping, calendar extraction, and Idle/Burst Control word interpretation. Client side channel data is provided with indicators for SOP, EOP, Data Valid, channel error, and channel identifier information.
Incoming Transmit Processor signals are received through a configurable client side packet interface with indicators provided for channel identifier, start of packet (SOP), end of packet (EOP), bytes valid, and data valid. Programmable burst control settings are provided for burst min, burst max, and burst short configurations. Channel data arrives and is processed before being placed into a channel FIFO where it is extracted as required by the XCI4FIC protocol engine. The protocol engine provides the insertion of idle/burst control words, scheduling, and lane striping functions using a configurable number of high speed lane processors/interfaces. Automatic or override flow control is provided for configurable in-band or out-of-band insertion. Each transmit high speed lane processor performs 64B/67B encoding, lane meta-frame insertion, and disparity operations. Lane diagnostics are provided including status and CRC-32 protection. Optional skip word insertion is provided for clock compensation purposes. A programmable lane test pattern generator is available for diagnostics and debug.
The Receive Processor accepts independent data on a configurable number of lanes. Each lane processor performs disparity operations, lane alignment/ deskew, and 64B/67B decoding. Receive Per-Lane state machines are provided for CDR lock, 64B/67B word boundary lock, and scrambler synchronization with programmable consequential action control. Lane status information is extracted and made available through the register interface provided. A variety of interrupts are reported to indicate status of incoming lane data. Lane test pattern checkers with pattern detection capability are provided for diagnostic and debug purposes. The receive processor protocol engine performs lane de-striping, calendar extraction, and Idle/Burst Control word interpretation. Client side channel data is provided with indicators for SOP, EOP, Data Valid, channel error, and channel identifier information.
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