The Xelic 100G OTN Segmentation and Reassembly Core provides support for the segmentation of ODUk/ODUj/ODUFlex frames into packets, and the reassembly of the ODUk/ODUj/ODUFlex streams from packets. This is intended to ultimately support the ability to perform OTN switching over a packet switch fabric. Support is included to allow for full ODUk/ODUj/ODUFlex timing transfer across the packet fabric, packet loss detection and replacement to insure integrity of ODUk/ODUj/ODUFlex framing, and packet delay variation compensation across the packet switch fabric. The supported content of the OTN client traffic is flexible, allowing for instance a single ODU4 client stream, 10xODU2 client streams, 80xODU0 client streams, etc.. Each different stream is associated with a unique Channel ID which gets transferred on both the Client and Fabric sides along with the data and data valid indicator. Client side data transfers use data valid signaling at clock rates up to 250 MHz to allow for flexible system clocking schemes. There is also, in accordance with the IA OIF-OFP-01.0 OTN Over Packet Fabric Protocol (OFP) Implementation Agreement November 2011, an input reference clock and synchronization pulse (8KHz) which are phase locked together externally. This reference clock is utilized for providing a mechanism for generating synchronous timestamp tracking as well as other internal processes relating to packet based decision generation/interpretation.
The XCO4SAR Transmit Processor provides Client Stream FIFO storage array for incoming channel based ODUk/ODUj/ODUflex streams from upstream OTN Framer/Multiplexer module(s). Using rate based information conveyed across the Tx Rate Interface, the Packet Scheduler will schedule a packet transmit request for that channel. Packet requests are handled in an orderly fashion. The Packet Scheduler issues the packet requests the Packet Formatter module, with the Packet Size Decision module indicating the scheduled packets size. The Packet Formatter responds by reading the appropriate amount of data from the corresponding Client Stream FIFO, inserting programmable packet OFP OH overhead bit fields such as User/Fabric OH bit field, calculate and insert the OFP OH odd parity bit, and insert timing based timestamp value, client status indicator, sequence count indicator, as well as Previous Packet Size indicators for up to previous 2 packets, and finally the Reserved1 bit field. Appropriate OH header bit fields are programmable through the register interface. Parity insertion and corruption are also supported for the OFP OH Pty field. Once the packet gets formed and ultimately transmitted the Packet Formatter will issue a done indicator back to the Packet Scheduler so that the next scheduled packet can be requested (designed such that no inherent wait states required in-between transmitted packets). The packet data gets transmitted across a straightforward packet bus interface, including SOP, EOP, and NUM_BYTES indicators (NUM_BYTES will only ever indicate partial bus fill coincident with EOP indication).
The XCO4SAR Receive Processor provides Packet FIFO storage array for incoming channel based OFP packets from upstream FIC (Packet Fabric Interface module/chip). The writing to the FIFOs will be controlled by the FIFO Write Control module in such a way as to insure that writes will begin only after the programmable packet age value (ie: timestamp difference between local timestamp value and packets timestamp value) is detected. This helps to align the packet channels which may have been delayed in different fashions across the packet switch fabric. Once enough OFP packet data is available within a particular channels FIFO storage, the Packet Scheduler will schedule a packet reformat request for that channel. Packet requests are handled in an orderly fashion, such that only one request can be queued per channel at any given time, and scheduled channel based requests are then handled in a round-robin fashion. The Packet Scheduler issues the packet requests to the Packet Reformatter module. The Packet Reformatter responds by reading the appropriate amount of data from the corresponding Client Stream FIFO, interpreting packet OFP OH overhead bit fields such as User/Fabric OH bit field, calculate and insert the OFP OH odd parity bit, and insert timing based timestamp value, client status indicator, sequence count indicator, as well as Previous Packet Size indicators for up to previous 2 packets, and finally the Reserved1 bit field. Appropriate OH header bit fields are accepted based upon configurable persistent packet count (ie: GENERIC setting defaulted to 3 consecutive packets), and the accepted values are reported via the register interface. Interrupts are available for both acceptance events and inconsistency events. Parity checking and interrupt/counts reporting is supported for the OFP OH Pty field. Once the packet gets interpreted, the Packet Reformatter module will issue a done indicator back to the Packet Scheduler, so that the next scheduled packet reformat can be requested (designed such that no inherent wait states required in-between received packets). The Packet Reformate also reports appropriate rate information across the Rx Rate Interface. Finally the resulting ODUk/ODUj/ODUflex stream data gets transmitted across a straightforward stream bus interface using valid indicator. Interrupts are also provided for various detections such as client signal status indication (based on incoming packet CSI bit field value) and packet fifo status conditions (ie: overflow/underflow).
Performance counters (configurable for error sync mode) are provided for the accumulation of detected (XCO4SAR transmit processor Tx Justification Interface signaling) positive, negative, and neutral justification request events, along with packet OFP OH parity errors detected, for all utilized time channels. Counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.
The XCO4SAR provides facility and terminal loopback modes of operation using Transmit and Receive Processor data path configurations for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included. A top level register control block is used for the configuration of subsystem modes of operation.